Methods and apparatus to transmit signals in isolated gate drivers
Methods, apparatus, systems and articles of manufacture are disclosed to transmit signal in isolated gate drivers. An example apparatus includes a first encoder including: an edge detector coupled to a first sensor; a first clock counter coupled to the edge detector; a first signal selector coupled to the first clock counter; and a first multiplexer including coupled to a signal generator, the first clock counter, and the first signal selector; and a second encoder including: a level detector coupled to a second sensor; a second clock counter coupled to the level detector; a second signal selector coupled to the level detector and the second clock counter; and a second multiplexer coupled to the first multiplexer, a reference voltage, the second signal selector, and a modulator.
1. An isolated gate driver circuit comprising:
(a) a low voltage stage having a pulse width modulation input, having a reset or enable input, having a low stage isolation barrier output, having a low stage isolation barrier input, having a first sensor output, and having a second sensor output;
(b) an isolation barrier including:
a first device having an input coupled to the low stage isolation barrier output and having an output; and
a second device having an output coupled to the low stage isolation barrier input and having an input; and
(c) a high voltage stage having a high stage isolation barrier input coupled to the first device output, having a high stage isolation barrier output coupled to the second device input, a supply voltage input, a driver output, a first sensor input, a second sensor input, and a third sensor input.
2. The isolated gate driver circuit of claim 1 in which the high voltage stage includes:
first sensor circuitry having an input coupled to the first sensor input and having a first sensor circuitry output;
second sensor circuitry having an input coupled to the second sensor input, having an input coupled to the first sensor circuitry output, and having a second sensor circuitry output; and
modulator circuitry having an input coupled to the second sensor circuitry output and having the high stage isolation barrier output coupled to the second device input.
3. The isolated gate driver circuit of claim 1 in which the high voltage stage includes:
first sensor circuitry having an input coupled to the first sensor input and having a first sensor circuitry output;
second sensor circuitry having an input coupled to the second sensor input, having an input coupled to the first sensor circuitry output, and having a second sensor circuitry output;
third sensor circuitry having a third sensor input coupled to the supply voltage input, having an input coupled to the second sensor circuitry output, and having a third sensor circuitry output;
modulator circuitry having an input coupled to the third sensor circuitry output and having the high stage isolation barrier output coupled to the second device input.
4. The isolated gate driver circuit of claim 1 in which the high voltage stage includes:
pulse width modulation circuitry having an input coupled to the first sensor input and having a pulse width modulation output;
fault sensor circuitry having an input coupled to the second sensor input an input coupled to the pulse width modulation output, and having a fault output; and
modulator circuitry having an input coupled to the fault output and having the high stage isolation barrier output coupled to the second device input.
5. The isolated gate driver circuit of claim 1 in which the high voltage stage includes:
pulse width modulation circuitry having an input coupled to the first sensor input and having a pulse width modulation output;
fault sensor circuitry having an input coupled to the second sensor input, having an input coupled to the pulse width modulation output, and having a fault output;
under voltage sensor circuitry having an input coupled to the supply voltage input, having an input coupled to the fault output, and having an under voltage output;
modulator circuitry having an input coupled to the under voltage output and having the high stage isolation barrier output coupled to the second device input.
6. The isolated gate driver circuit of claim 1 in which the high voltage stage includes pulse width modulation circuitry having an analog input coupled to the first sensor input and including signal generator circuitry having an input coupled to the analog input and having a digital pulse width modulation output, the signal generator circuitry providing a digital pulse width modulation signal at a first frequency at the digital output.
7. The isolated gate driver of claim 6 in which the first frequency is in the range of 100s of kilohertz.
8. The isolated gate driver circuit of claim 6 in which the high voltage stage includes fault encoder circuitry having an input coupled to the second sensor input, having an oscillator signal input at a second frequency different from the first frequency, having an input coupled to the digital pulse width modulation output, and having a fault output.
9. The isolated gate driver of claim 6 in which the second frequency is in the range of 10s of MegaHertz.
10. The isolated gate driver circuit of claim 8 in which the fault encoder circuitry includes:
an oscillator having an output coupled to the oscillator signal input;
edge detector circuitry having an input coupled to the second sensor input, having an input coupled to the oscillator signal input, and having an edge detect output;
first clock counter circuitry having an input coupled to the edge detect output, having an input coupled to the oscillator signal input, having a first count input, and having a second frequency clock signal output;
signal selector circuitry having an input coupled to the oscillator signal input, an input coupled to the clock counter circuitry, and having a first select output; and
first multiplexer circuitry having an input coupled to the digital pulse width modulation output, having an input coupled to the second frequency clock signal output, having an input coupled to the first select output, and having a first multiplexer output.
11. The isolated gate driver circuit of claim 8 in which the first count input equals 36.
12. The isolated gate driver circuit of claim 8 in which the high voltage stage includes:
under voltage encoder circuitry having an input coupled to the supply voltage input, having an input coupled to the fault output, having an oscillator signal input at the second frequency, and having an under voltage output; and
modulator circuitry having an input coupled to the under voltage output and having the high stage isolation barrier output coupled to the second device input.
13. The isolated gate driver circuit of claim 12 in which the under voltage encoder circuitry includes:
level detector circuitry having an input coupled to the supply voltage input, having an input coupled to the oscillator signal input, and having an event output;
second clock counter circuitry having an input coupled to the oscillator signal input, having an input coupled to the event output, having a second count input, and having a second clock output;
selector circuitry having a first input coupled to the event output, having an input coupled to the second clock output, and having a second select output; and
second multiplexer circuitry having an input coupled to the first multiplexer output, having an input tied to a logic state, having a control input coupled to the second select output, and having a modulator output.
14. The isolated gate driver of claim 13 in which the count input equals 240.
15. The isolated gate driver of claim 13 including modulator circuitry having an input coupled go the modulator output and having an output coupled to the a high stage isolation barrier output.