Methods for adjusting memory device refresh operations based on memory device temperature, and related memory devices and systems
Methods of operating a memory device are disclosed. A method may include determining an operating temperature of a memory bank of a memory device. The method may also include adjusting at least one refresh interval for the memory bank based on the operating temperature of the memory bank. Further, the method may include skipping at least one refresh of the memory bank based on at least one of the operation temperature of the memory bank and a number of active signals received at the memory bank. A memory device and an electronic system are also described.
1. A method of operating a memory device, comprising:
determining an operating temperature of a memory bank of a memory device;
adjusting at least one refresh interval for the memory bank based on the operating temperature of the memory bank; and
skipping at least one refresh of the memory bank based on at least one of the operating temperature of the memory bank and a number of active signals received at the memory bank, wherein skipping the at least one refresh comprises skipping the at least one refresh such that one of: one refresh command out of three refresh commands are skipped; one refresh command out of two refresh commands are skipped; two refresh commands out of three refresh commands are skipped; and three refresh commands out of four refresh commands are skipped.
2. The method of claim 1 , further comprising setting a skip rate for refreshes for the memory bank.
3. The method of claim 2 , wherein setting a skip rate comprises setting the skip rate such that for every twelve refresh commands one of: four refresh commands are skipped; six refresh commands are skipped; eight refresh commands are skipped; and nine refresh commands are skipped.
4. The method of claim 1 , wherein determining the operating temperature of the memory bank comprises determining the operating temperature via at least one of a temperature sensor of the memory device and a mode register of the memory device.
5. The method of claim 4 , wherein adjusting the at least one refresh interval for the memory bank comprises adjusting at least one of an auto refresh interval and a row hammer refresh steal rate for the memory bank.
6. The method of claim 1 , wherein skipping at least one refresh comprises:
skipping a first number of refreshes during a refresh interval in response to the operating temperature being less than or equal to a first threshold temperature;
skipping a second number of refreshes in response to the operating temperature being less than or equal to a second threshold temperature, the second threshold temperature less than the first threshold temperature; and
skipping a third number of refreshes in response to the operating temperature being less than or equal to a third threshold temperature, the third threshold temperature less than the second threshold temperature.
7. The method of claim 1 , wherein adjusting at least one refresh interval for the memory bank comprise adjusting a refresh rate for the memory bank, and skipping at least one refresh comprises selecting a skip rate based at least partially on the refresh rate for the memory bank.
8. The method of claim 1 , wherein adjusting the at least one refresh interval for the memory bank comprises adjusting a row hammer refresh steal rate for the memory bank based the operating temperature of the memory bank and the number of active signals received at the memory bank.
9. A memory device, comprising:
a memory array including at least one memory bank; and
at least one controller coupled to the memory array and configured to:
set a refresh interval for the memory bank based on an operating temperature of the memory bank;
set a row hammer refresh steal rate for the memory bank based on the operating temperature of the memory bank; and
set a refresh skip rate for the memory bank based the operating temperature of the memory bank.
10. The memory device of claim 9 , wherein the at least one controller is configured to:
set the refresh skip rate to a first value in response to the operating temperature being less than or equal to a first threshold temperature;
set the refresh skip rate to a second value in response to the operating temperature being less than or equal to a second threshold temperature, the second threshold temperature less than the first threshold temperature; and
set the refresh skip rate to a third value in response to the operating temperature being less than or equal to a third threshold temperature, the third threshold temperature less than the second threshold temperature.
11. The memory device of claim 10 , wherein the first threshold temperature is approximately 85° Celsius (C), the second threshold temperature is approximately 60° C., and the third threshold temperature is approximately 45° C.
12. The memory device of claim 9 , wherein the at least one controller includes:
a counter configured to generate a count indicative of a number of refresh commands received from an external device at the memory bank;
a first decoder and multiplexer unit coupled to an output of the counter and configured to:
store a first value based on a selected mode of operation; and
generate a first pulse signal in response to the count being equal to the first value;
a flip-flop coupled to an output of the first decoder and multiplexer unit and configured to generate an asserted enable signal in response to the first pulse signal; and
a second decoder and multiplexer unit coupled to the output of the counter configured to:
store a second value based on a number of desired cycles in a refresh interval; and
generate a second pulse signal in response to the count being equal to the second value, the second pulse configured to reset the flip-flop and the counter.
13. The memory device of claim 9 , wherein the at least one controller is further configured to set the row hammer refresh steal rate for the memory bank based an amount of activity associated with the memory bank.
14. The memory device of claim 13 , wherein the at least one controller includes:
a counter configured to generate a count value indicative of asserted active signal commands received at the memory bank; and
at least one circuit configured to set the row hammer refresh steal rate for the memory bank based on the count value.
15. The memory device of claim 14 , wherein the at least one controller further includes a counter selector configured to select a subset of bits of the count value based on the operating temperature of the memory bank.
16. An electronic system, comprising:
at least one input device;
at least one output device;
at least one processor device operably coupled to the input device and the output device; and
at least one memory device operably coupled to the at least one processor device and comprising:
a memory array; and
a controller coupled to the memory array and configured to:
control a refresh interval for the memory array based on an operating temperature of the memory array;
control a row hammer refresh steal rate based on the operating temperature of the memory array; and
control a refresh skip rate for the memory array based on at least one of the refresh interval and the operating temperature of the memory array.
17. The electronic system of claim 16 , wherein the controller is further configured to adjust the refresh interval in response to the operating temperature being less than a threshold temperature.
18. The electronic system of claim 16 , wherein the controller is further configured to adjust the refresh skip rate in response to the operating temperature being less than a threshold temperature.