Deep trench isolation structure and method of making the same

1. A semiconductor structure comprising:

at least a first semiconductor device located on a first semiconductor substrate material portion located in a high voltage region;

at least a second semiconductor device located on a second semiconductor substrate material portion located outside the high voltage region;

a first moat trench isolation structure electrically insulating the first semiconductor substrate material portion from the second semiconductor substrate material portion; and

a second moat trench isolation structure electrically insulating the first semiconductor substrate material portion from the second semiconductor substrate material portion and laterally surrounding the first semiconductor substrate material portion and laterally surrounded by the first moat trench isolation structure.

2. The semiconductor structure of claim 1 , further comprising a buried insulator layer contacting bottom surfaces of the first semiconductor substrate material portion, the second semiconductor substrate material portion, the first moat trench isolation structure, and the second moat trench isolation structure.

3. The semiconductor structure of claim 2 , further comprising a handle substrate underlying the buried insulator layer, wherein the buried insulator layer comprises silicon oxide and has a thickness in a range from 50 nm to 500 nm.

4. The semiconductor structure of claim 1 , wherein the first moat trench isolation structure comprises dielectric sidewall spacers and a conductive fill material portion located between the dielectric sidewall spacers.

5. The semiconductor structure of claim 4 , further comprising first conformal diffusion barrier layers located between sidewalls of the first moat trench isolation structures and a respective one of the dielectric sidewall spacers.

6. The semiconductor structure of claim 4 , wherein the second moat trench isolation structure is filled with at least one dielectric material.

7. The semiconductor structure of claim 6 , wherein the second moat trench isolation structure comprises a dielectric moat trench fill structure having a same material composition as the dielectric sidewall spacers and having a lateral thickness that is greater than a lateral thickness of the dielectric sidewall spacers and is less than twice the lateral thickness of the dielectric sidewall spacers.

8. The semiconductor structure of claim 1 , wherein:

the at least first semiconductor device comprises a bipolar-CMOS-DMOS (BCD) device and has an operating voltage in a range from 50 volts to 1,000 volts.

9. A semiconductor structure comprising:

at least one first semiconductor device located on a first semiconductor substrate material portion located in a high voltage region;

at least one second semiconductor device located on a second semiconductor substrate material portion located in a low voltage region; and

a set of at least two nested moat trench isolation structures laterally surrounding the high voltage region and electrically insulating the high voltage region from the low voltage region,

wherein a first of the at least two moat trench isolation structures is filled with at least one dielectric material and a second of the at least two moat trench isolation structures comprises an inner dielectric sidewall spacer, an outer dielectric sidewall spacer, and a conductive moat fill material portion located between the inner dielectric sidewall spacer and the outer dielectric sidewall spacer.

10. The semiconductor structure of claim 9 , wherein the conductive moat fill material portion comprises polysilicon.

11. The semiconductor structure of claim 9 , wherein a width of the second of the at least two moat trench isolation structures is at least twice a width of the first of the at least two moat trench isolation structures.

12. The semiconductor device of claim 9 , wherein the high voltage region comprises a power region, and the low voltage region comprises a digital region and an analog region.