Image sensor with dummy lines for minimizing fixed pattern noise (FPN) and electronic apparatus including the same

1. An image sensor, comprising:

a plurality of pixels, each pixel of the plurality of pixels including a photodiode, which is coupled to a transfer transistor, which is coupled to a reset transistor, which is coupled to a source-follower transistor, which is coupled to a selection transistor;

a plurality of first interconnection lines connected to a gate of the transfer transistor, a gate of the reset transistor, and a gate of the selection transistor, the plurality of first interconnection lines extending in a first direction; and

a plurality of second interconnection lines connected to a source region of the selection transistor, the plurality of second interconnection lines extending in a second direction that intersects the first direction,

wherein the plurality of second interconnection lines includes dummy lines on a peripheral area that is outside of a pixel area in which the pixels are located.

2. The image sensor as claimed in claim 1 , wherein:

the plurality of second interconnection lines have a same length in the second direction.

3. The image sensor as claimed in claimed in claim 1 , wherein:

the plurality of second interconnection lines have a same capacitance.

4. The image sensor as claimed in claim 1 , wherein:

at least one first interconnection line of the plurality of first interconnection lines has a length that is different from a length of remaining first interconnection lines of the plurality of first interconnection lines.

5. The image sensor as claimed in claim 1 , further comprising:

a first semiconductor chip that includes the pixel area and the peripheral area; and

a second semiconductor chip under the first semiconductor chip, the second semiconductor chip including logic devices configured to process signals,

wherein:

the plurality of first interconnection lines are row lines, and

the plurality of second interconnection lines are column lines.

6. The image sensor as claimed in claim 5 , wherein:

through vias connected to the plurality of second interconnection lines are located in the peripheral area, the through vias being arranged along the first direction to be periodically farther away from the pixel area in the second direction,

the plurality of second interconnection lines are alternately connected to one of the through vias located on an upper side of the second direction and another of the through vias located on a lower side of the second direction, the plurality of second interconnection lines including effective lines from the pixel area to the through vias, and

the dummy lines are connected to the effective lines and extend beyond the through vias in the second direction.

7. The image sensor as claimed in claim 6 , wherein:

every n through vias form a group along the first direction, n being a natural number equal to or greater than 2,

a first through via of the through vias included in any one group is located closest to the pixel area, and an n-th through via of the through vias included in the any one group is located farthest from the pixel area,

one of the dummy lines corresponding to the first through via extends a longest length, and

no dummy line corresponding to the n-th through via exists or a dummy line corresponding to the n-th through via extends a shortest length.

8. The image sensor as claimed in claim 5 , wherein:

vertical contacts, middle interconnections, and through vias are in the peripheral area, the vertical contacts being connected to the plurality of second interconnection lines, the middle interconnections being at a different layer from the plurality of second interconnection lines and connected to the vertical contacts, the middle interconnections extending in the first direction, the through vias being connected to the middle interconnections and arranged in a line in the second direction,

the vertical contacts are arranged along the first direction to be periodically farther away from the pixel areas in the second direction,

the plurality of second interconnection lines are alternately connected to a vertical contact located on an upper side of the second direction and a vertical contact of a lower side of the second direction, the plurality of second interconnection lines including effective lines from the pixel area to the vertical contact, and

the dummy lines are connected to the effective lines and extend beyond the vertical contacts in the second direction.

9. The image sensor as claimed in claim 8 , wherein:

every n vertical contacts repetitively form groups along the first direction, n being a natural number equal to or greater than 2,

a first vertical contact of the vertical contacts included in any one group is located closest to the pixel area, and an n-th vertical contact of the vertical contacts included in the any one group is located farthest from the pixel area,

one of the dummy lines corresponding to the first vertical contact extends a longest length, and

no dummy line corresponding to the n-th vertical contact exists or a dummy line corresponding to the n-th vertical contact extends a shortest length.

10. The image sensor as claimed in claim 8 , further comprising an additional dummy line connected to any one of the middle interconnections, wherein:

every n middle interconnections form a group, and every n through vias form a group,

a first middle interconnection of the middle interconnections included in any one group is longest along the second direction, and an n-th middle interconnection of the middle interconnections included in the any one group is shortest along the second direction,

an additional dummy line corresponding to the n-th middle interconnection extends a longest length, and

no additional dummy line corresponding to the first middle interconnection exists or an additional dummy line corresponding to the first middle interconnection extends a shortest length.

11. The image sensor as claimed in claim 5 , wherein:

through vias are in the peripheral area, the through vias being connected to the plurality of second interconnection lines and extend in the second semiconductor chip,

the plurality of second interconnection lines are connected to an analog-to-digital converter through the through vias, the analog-to-digital converter being located on the second semiconductor chip.