Threshold voltage adjustment by inner spacer material selection
Semiconductor devices and methods of forming the same include partially etching sacrificial layers in a first stack of alternating sacrificial layers and channel layers to form first recesses. A first inner spacer sub-layer is formed in the first recesses from a first dielectric material. A second inner spacer sub-layer is formed in the first recesses from a second dielectric material, different from the first dielectric material. The sacrificial layers are etched away. The first inner spacer sub-layer is etched away. A gate stack is formed on and around the channel layers and in contact with the second inner spacer sub-layer.
1. A method of forming a semiconductor device, comprising:
partially etching sacrificial layers in a first stack of alternating sacrificial layers and channel layers to form first recesses;
forming a first inner spacer sub-layer in the first recesses from a first dielectric material;
forming a second inner spacer sub-layer in the first recesses from a second dielectric material, different from the first dielectric material;
etching away the sacrificial layers;
etching away the first inner spacer sub-layer; and
forming a gate stack on and around the channel layers and in contact with the second inner spacer sub-layer.
2. The method of claim 1 , further comprising forming a third inner spacer sub-layer in the first recesses.
3. The method of claim 2 , wherein the third inner spacer sub-layer is formed from the first dielectric material.
4. The method of claim 1 , wherein the first dielectric material is silicon nitride and the second dielectric material is silicon dioxide.
5. The method of claim 1 , further comprising partially etching sacrificial layers in a second stack of alternating sacrificial layers and channel layers to form second recesses, wherein forming the first inner spacer sub-layer in the first recesses comprises a deposition process that deposits the first dielectric material in the first recesses and the second recesses.
6. The method of claim 5 , further comprising masking the second stack after the deposition process.
7. The method of claim 6 , further comprising etching the first dielectric material on the first stack with a first timed etch process after masking the second stack.
8. The method of claim 7 , further comprising unmasking the second stack and etching the first dielectric material on the first stack and the second stack with a second timed etch process.
9. A method of forming a semiconductor device, comprising:
partially etching sacrificial layers in a first stack of alternating sacrificial layers and channel layers to form first recesses;
forming a first inner spacer sub-layer in the first recesses from a first dielectric material;
forming a second inner spacer sub-layer in the first recesses from a second dielectric material, different from the first dielectric material;
forming a third inner spacer sub-layer in the first recesses from the first dielectric material;
etching away the sacrificial layers;
etching away the first inner spacer sub-layer; and
forming a gate stack on and around the channel layers and in contact with the second inner spacer sub-layer.
10. The method of claim 9 , wherein the first dielectric material is silicon nitride and the second dielectric material is silicon dioxide.
11. The method of claim 9 , further comprising partially etching sacrificial layers in a second stack of alternating sacrificial layers and channel layers to form second recesses, wherein forming the first inner spacer sub-layer in the first recesses comprises a deposition process that deposits the first dielectric material in the first recesses and the second recesses.
12. The method of claim 11 , further comprising masking the second stack after the deposition process.
13. The method of claim 12 , further comprising etching the first dielectric material on the first stack with a first timed etch process after masking the second stack.
14. The method of claim 13 , further comprising unmasking the second stack and etching the first dielectric material on the first stack and the second stack with a second timed etch process.
15. An integrated chip, comprising:
a first semiconductor device, comprising:
a plurality of vertically aligned first channel layers;
first inner spacers between respective pairs of the first channel layers, formed from a single layer of a first dielectric material; and
a first gate stack in contact with the first channel layers and the first inner spacers; and
a second semiconductor device, comprising:
a plurality of vertically aligned second channel layers;
second inner spacers between respective pairs of the second channel layers, each inner spacer including an inner layer formed from a second dielectric material and an outer layer formed from the first dielectric material; and
a second gate stack in contact with the second channel layers and the inner layers of the second inner spacers.
16. The integrated chip of claim 15 , wherein the second dielectric material is silicon dioxide and the first dielectric material is silicon nitride.
17. The integrated chip of claim 16 , wherein the inner layers are in direct contact with the gate stack and the outer layers, and wherein the outer layers are in direct contact with a source/drain structure.
18. The integrated chip of claim 15 , wherein the first inner spacers completely fill a space defined by side surfaces of the first channel layers and adjacent side surfaces of the first gate stack.
19. The integrated chip of claim 15 , wherein the first and second semiconductor devices each further comprise gate sidewalls over a topmost set of respective inner spacers.
20. The integrated chip of claim 15 , wherein the first semiconductor device comprises first top spacers that extend over the first inner spacers and a portion of the first gate stack and wherein the second semiconductor device comprises second top spacers that extend over the second inner spacers and a portion of the second gate stack.