Transistors with stacked semiconductor layers as channels
View Patent ↗A method of forming a semiconductor device includes depositing a p-type semiconductor layer over a portion of a semiconductor substrate, depositing a semiconductor layer over the p-type semiconductor layer, wherein the semiconductor layer is free from p-type impurities, forming a gate stack directly over a first portion of the semiconductor layer, and etching a second portion of the semiconductor layer to form a trench extending into the semiconductor layer. At least a surface of the p-type semiconductor layer is exposed to the trench. A source/drain region is formed in the trench. The source/drain region is of n-type.
1. A device comprising:
a bulk semiconductor substrate;
a semiconductor stack comprising:
a first semiconductor layer and a second semiconductor layer over the bulk semiconductor substrate, wherein the first semiconductor layer and the second semiconductor layer have first p-type impurity concentrations; and
a third semiconductor layer, wherein the third semiconductor layer is between and physically contacting the first semiconductor layer and the second semiconductor layer, wherein a second p-type impurity concentration in the third semiconductor layer is lower than the first p-type impurity concentrations;
a gate stack on the semiconductor stack; and
a source/drain region on a side of, and contacting the semiconductor stack.
2. The device of claim 1 , wherein the second p-type impurity concentration in the third semiconductor layer is at least one order lower than the first p-type impurity concentrations.
3. The device of claim 2 , wherein the second p-type impurity concentration in the third semiconductor layer is at least two orders lower than the first p-type impurity concentrations.
4. The device of claim 1 , wherein the source/drain region is an n-type region.
5. The device of claim 1 further comprising:
dielectric isolation regions over the bulk semiconductor substrate, wherein the semiconductor stack is between opposing portions of the dielectric isolation regions, and wherein a top portion of the semiconductor stack is higher than top surfaces of the dielectric isolation regions.
6. The device of claim 1 , wherein the semiconductor stack further comprises:
a fourth semiconductor layer over the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer, wherein a third p-type impurity concentration in the fourth semiconductor layer is lower than the first p-type impurity concentrations.
7. The device of claim 6 , wherein the gate stack physically contacts a top surface of the fourth semiconductor layer.
8. A semiconductor device comprising:
a bulk semiconductor substrate;
a first plurality of semiconductor layers over the bulk semiconductor substrate, wherein the first plurality of semiconductor layers have first p-type impurity concentrations;
a second plurality of semiconductor layers, wherein the first plurality of semiconductor layers and the second plurality of semiconductor layers form a stack of layers, and are allocated alternatingly, wherein each of the second plurality of semiconductor layers has a second p-type impurity concentration greater than the first p-type impurity concentrations of an immediate overlying one and an immediate underlying one of the second plurality of semiconductor layers;
a gate stack on a top surface and sidewalls of the stack of layers; and
a source/drain region on a side of, and contacting the stack of layers.
9. The semiconductor device of claim 8 , wherein the second p-type impurity concentration of each of the second plurality of semiconductor layers is greater than the first p-type impurity concentration of each of the first plurality of semiconductor layers.
10. The semiconductor device of claim 8 , wherein the second p-type impurity concentration of each of the second plurality of semiconductor layers is greater than the first p-type impurity concentrations of an immediate overlying one and an immediate underlying one of the first plurality of semiconductor layers by at least one order.
11. The semiconductor device of claim 8 , wherein the source/drain region is n-type.
12. The semiconductor device of claim 8 , wherein the source/drain region has a sidewall contacting at least one of the first plurality of semiconductor layers and one of the second plurality of semiconductor layers to form vertical interfaces.
13. A semiconductor device comprising:
isolation regions extending into a semiconductor substrate;
a semiconductor region between the isolation regions, wherein a first top surface of the semiconductor region is higher than second top surfaces of the isolation regions, and the semiconductor region comprises:
a first intrinsic semiconductor layer, the first intrinsic semiconductor layer being free from p-type impurities; and
a first p-type semiconductor layer over and contacting the first intrinsic semiconductor layer;
a gate stack on the semiconductor region; and
a source/drain region extending into the semiconductor region, wherein the source/drain region contacts the first p-type semiconductor layer, and the source/drain region is an n-type region.
14. The semiconductor device of claim 13 , wherein an entirety of the source/drain region is higher than the first p-type semiconductor layer.
15. The semiconductor device of claim 13 , wherein the source/drain region extends into the first p-type semiconductor layer, and the source/drain region comprises a bottom surface spaced apart from a top surface of the first intrinsic semiconductor layer by a portion of the first p-type semiconductor layer.
16. The semiconductor device of claim 13 , wherein the source/drain region comprises a bottom surface contacting a top surface of the first intrinsic semiconductor layer.
17. The semiconductor device of claim 16 , wherein the source/drain region extends into, and contacts a sidewall of, the first intrinsic semiconductor layer.
18. The semiconductor device of claim 13 , wherein the semiconductor region further comprises a second intrinsic semiconductor layer over and contacting the first p-type semiconductor layer.
19. The semiconductor device of claim 18 , wherein the semiconductor region further comprises:
a second p-type semiconductor layer over and contacting the second intrinsic semiconductor layer; and
a third intrinsic semiconductor layer over and contacting the second p-type semiconductor layer.
20. The semiconductor device of claim 13 , wherein the gate stack contacts sidewalls of a top portion of the semiconductor region.