Formation of stacked vertical transport field effect transistors
View Patent ↗A semiconductor device structure and method for fabricating the same. The semiconductor device structure includes a first vertical transport field effect transistor (VTFET) comprising a first semiconductor fin and a second VTFET stacked on the first VTFET. The second VTFET includes a second semiconductor fin that is separate and distinct from the first semiconductor fin. At least one insulating layer is disposed on a top surface of the first VTFET. The second VTFET is disposed on the at least one insulating layer. The method includes forming a first vertical VTFET on a first substrate and bonding a second substrate to and on top of the first VTFET. A second VTFET is formed on the second substrate.
1. A semiconductor device structure comprising at least:
a first vertical transport field effect transistor (VTFET) comprising a first semiconductor fin;
a second VTFET stacked on the first VTFET and comprising a second semiconductor fin that is separate and distinct from the first semiconductor fin; and
at least one insulating layer formed on a top surface of the first VTFET, wherein the second VTFET is formed on the at least one insulating layer, and wherein the first semiconductor fin is insulated from the second semiconductor fin by the at least one insulating layer.
2. The semiconductor device structure of claim 1 , wherein the first VTFET and the second VTFET comprise one of a same doping type or a different doping type.
3. The semiconductor device structure of claim 1 , wherein first VTFET comprises
a first bottom source/drain in contact with a substrate and sidewalls of the first semiconductor fin; and
a first bottom insulating layer in contact with the first bottom source/drain and sidewalls of the first semiconductor fin,
wherein the second VTFET comprises
a second bottom source/drain in contact with the at least one insulating layer and sidewalls of the second semiconductor fin; and
a second bottom insulating layer in contact with the second bottom source/drain and sidewalls of the second semiconductor fin.
4. The semiconductor device structure of claim 3 , wherein first VTFET further comprises
a first gate structure in contact with the first bottom insulating layer and sidewalls of the first semiconductor fin; and
a first top insulating layer in contact with the first gate structure and sidewalls of the first semiconductor fin,
wherein the second VTFET comprises
a second gate structure in contact with the second bottom insulating layer and sidewalls of the second semiconductor fin; and
a second top insulating layer in contact with the second gate structure and sidewalls of the second semiconductor fin.
5. The semiconductor device structure of claim 4 , wherein first VTFET further comprises
a first top source/drain in contact with the first top insulating layer and the first semiconductor fin,
wherein the second VTFET comprises
a second top source/drain in contact with the second top insulating layer and the second semiconductor fin.
6. The semiconductor device structure of claim 5 , wherein first VTFET further comprises
a first encapsulation layer in contact with the first gate structure and first top insulating layer,
wherein the second VTFET comprises
a second encapsulation layer in contact with the second gate structure and second top insulating layer.
7. An integrated circuit comprising:
a stacked vertical transport field effect transistor (VTFET) device, wherein the stacked VTFET device comprises
a first vertical transport field effect transistor (VTFET) comprising a first semiconductor fin;
a second VTFET stacked on the first VTFET and comprising a second semiconductor fin that is separate and distinct from the first semiconductor fin; and
at least one insulating layer formed on a top surface of the first VTFET, wherein the second VTFET is formed on the at least one insulating layer, and wherein the first semiconductor fin is insulated from the second semiconductor fin by the at least one insulating layer.
8. The integrated circuit of claim 7 , wherein the first VTFET and the second VTFET comprise one of a same doping type or a different doping type.
9. The integrated circuit of claim 7 , wherein first VTFET comprises
a first bottom source/drain in contact with a substrate and sidewalls of the first semiconductor fin; and
a first bottom insulating layer in contact with the first bottom source/drain and sidewalls of the first semiconductor fin,
wherein the second VTFET comprises
a second bottom source/drain in contact with the at least one insulating layer and sidewalls of the second semiconductor fin; and
a second bottom insulating layer in contact with the second bottom source/drain and sidewalls of the second semiconductor fin.
10. The integrated circuit of claim 9 , wherein first VTFET further comprises
a first gate structure in contact with the first bottom insulating layer and sidewalls of the first semiconductor fin; and
a first top insulating layer in contact with the first gate structure and sidewalls of the first semiconductor fin,
wherein the second VTFET comprises
a second gate structure in contact with the second bottom insulating layer and sidewalls of the second semiconductor fin; and
a second top insulating layer in contact with the second gate structure and sidewalls of the second semiconductor fin.
11. The integrated circuit of claim 10 , wherein first VTFET further comprises
a first top source/drain in contact with the first top insulating layer and the first semiconductor fin,
wherein the second VTFET comprises
a second top source/drain in contact with the second top insulating layer and the second semiconductor fin.
12. The integrated circuit of claim 11 , wherein first VTFET further comprises
a first encapsulation layer in contact with the first gate structure and first top insulating layer,
wherein the second VTFET comprises
a second encapsulation layer in contact with the second gate structure and second top insulating layer.