Method for forming source/drain contacts
Semiconductor devices and methods of forming the same are provided. In one embodiments, the method includes providing a structure that includes a substrate, a first gate structure and a second gate structure over the substrate, a first source/drain (S/D) feature comprising silicon adjacent to the first gate structure, a second S/D feature comprising silicon germanium (SiGe) adjacent to the second gate structure; and one or more dielectric layers over sidewalls of the first and second gate structures and over the first and second S/D features. The method further includes etching the one or more dielectric layers to form openings exposing the first and second S/D features, forming a masking layer over the first S/D feature, implanting gallium (Ga) into the second S/D feature while the masking layer is over the first S/D feature, removing the masking layer; and etching the first and second S/D features with an oxygen-atom-containing etchant.
1. A method of forming a semiconductor device, the method comprising:
providing a structure that includes:
a substrate;
a first gate structure and a second gate structure over the substrate;
a first source/drain (S/D) feature comprising silicon adjacent to the first gate structure;
a second S/D feature comprising silicon germanium (SiGe) adjacent to the second gate structure; and
one or more dielectric layers over sidewalls of the first and second gate structures and over the first and second S/D features;
etching the one or more dielectric layers to form openings exposing the first and second S/D features;
forming a masking layer over the first S/D feature;
implanting gallium (Ga) into the second S/D feature while the masking layer is over the first S/D feature, thereby producing a gallium-containing implant layer over the second S/D feature;
removing the masking layer; and
etching the first and second S/D features with an oxygen-atom-containing etchant, thereby converting a top portion of the gallium-containing implant layer into a gallium oxide containing layer while a bottom portion of the gallium-containing implant layer remains on the second S/D feature.
2. The method of claim 1 , further comprising doping the second S/D feature with boron (B) while the masking layer is over the first S/D feature.
3. The method of claim 1 , further comprising:
forming a protective dielectric layer over the first and second S/D features.
4. The method of claim 1 , further comprising annealing the second S/D feature to activate gallium (Ga).
5. The method of claim 4 , further comprising, after annealing the second S/D feature to activate gallium (Ga), forming a protective dielectric layer over sidewalls of the openings exposing the first and second S/D features.
6. The method of claim 1 , wherein the oxygen-atom-containing etchant is a gas mixture of sulfur fluoride (SF 6 ) and oxygen (O 2 ).
7. The method of claim 1 , wherein the oxygen-atom-containing etchant is a potassium hydroxide (KOH) solution.
8. The method of claim 1 , further comprising removing the gallium oxide containing layer.
9. The method of claim 8 , further comprising, after the removing of the gallium oxide containing layer, depositing a metal layer over the first and second S/D features.
10. The method of claim 1 , wherein the implanting of the gallium (Ga) uses a doping energy ranging from 1 keV to 10 keV and a doping dose ranging from 1E15 cm −2 to 1E17 cm −2 .
11. The method of claim 1 , wherein the etching of the first and second S/D features recesses the first S/D feature deeper than the second S/D feature.
12. The method of claim 2 , wherein the doping of the second S/D feature with boron (B) is prior to the implanting of gallium (Ga) into the second S/D feature.
13. A method of forming a semiconductor device, the method comprising:
providing a structure that includes:
a substrate;
a first gate structure and a second gate structure over the substrate;
a first source/drain (S/D) feature comprising n-type doped silicon adjacent to the first gate structure;
a second S/D feature comprising silicon germanium (SiGe) adjacent to the second gate structure; and
one or more dielectric layers over sidewalls of the first and second gate structures and over the first and second S/D features;
etching the one or more dielectric layers to expose the first and second S/D features;
forming a masking layer over the first S/D feature;
implanting the second S/D feature with gallium (Ga) while the masking layer is over the first S/D feature, resulting in a gallium-containing implant layer over the second S/D feature;
removing the masking layer;
etching the first and second S/D features with an oxygen-atom-containing etchant, resulting in conversion of a top portion of the gallium-containing implant layer into a gallium oxide containing layer while a bottom portion of the gallium-containing implant layer remains over the second S/D feature;
removing the gallium oxide containing layer;
depositing a metal layer over the first S/D feature and the bottom portion of the gallium-containing implant layer over the second S/D feature; and
annealing the first and second S/D features.
14. The method of claim 13 , further comprising doping the second S/D feature with boron (B) while the masking layer is over the first S/D feature.
15. The method of claim 13 , further comprising annealing the second S/D feature to activate gallium (Ga).
16. The method of claim 13 , wherein the oxygen-atom-containing etchant comprises a gas mixture of Sulfur fluoride (SF 6 ) and oxygen (O 2 ) or a potassium hydroxide (KOH) solution.
17. The method of claim 13 , wherein the implanting of the second S/D feature with gallium (Ga) uses a doping energy ranging from 1 keV to 10 keV and a doping dose ranging from 1E15 cm −2 to 1E17 cm −2 .
18. A method of forming a semiconductor device, the method comprising:
providing a structure that includes:
a substrate;
a first gate structure and a second gate structure over the substrate;
a first source/drain (S/D) feature adjacent to the first gate structure; and
a second S/D feature adjacent to the second gate structure;
forming a masking layer over the first S/D feature;
implanting dopants into the second S/D feature while the masking layer is over the first S/D feature, thereby forming a dopant-containing implant layer over the second S/D feature;
removing the masking layer;
forming a protective dielectric layer over sidewalls of the first and second gate structures and over the first and second S/D features;
anisotropically etching the protective dielectric layer to expose the first and second S/D features;
after the anisotropically etching of the protective dielectric layer, performing a first etching process in recessing the first and second S/D features with an oxygen-atom-containing etchant, thereby converting a top portion of the dopant-containing implant layer into a dopant-containing oxide layer; and
after the performing of the first etching process, performing a second etching process in removing the dopant-containing oxide layer.
19. The method of claim 18 , wherein the dopants comprise gallium (Ga).
20. The method of claim 18 , wherein the recessing of the first and second S/D features includes performing a selective etching process to the first and second S/D features with the oxygen-atom-containing etchant, and wherein the first S/D feature is recessed more than the second S/D feature.