IP Library › Granted Patent US 11,037,931
Granted Patent B2
US 11,037,931 · App. 16/679,317 · Granted Jun 15, 2021

Method for fabricating semiconductor device

Inventors: Keewoung Choi (Singapore, SG); Hasung Lee (Singapore, SG); Sung-Ki Kim (Singapore, SG)
Assignee: XIA TAI XIN SEMICONDUCTOR (QING DAO) LTD.
H01L27/10814H01L27/10823H01L27/10852H01L27/10897H01L28/75
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Quick Facts
Patent No.
US 11,037,931
App. No.
16/679,317
Granted
Jun 15, 2021
Kind
B2
Abstract

The instant disclosure discloses method comprising receiving a substrate; disposing a dielectric layer over the substrate; disposing a metallic material on the dielectric layer; disposing a passivation layer on top surface of the metallic material; and performing an alloy layer formation process to dispose a SiGe layer across top surface of the passivation layer.

Claims (18)

1. A method, comprising:

receiving a substrate;

disposing a plurality of lower electrodes over the substrate, wherein each of the plurality of lower electrodes has a U-shaped profile in a cross section thereof in a direction parallel to a thickness direction of the substrate, each of the plurality of the lower electrodes defines an interior surface and an exterior surface opposing to the interior surface;

disposing a dielectric layer over the substrate, wherein the dielectric layer conformally covers both the interior surface and the exterior surface of each of the plurality of lower electrodes;

disposing a metallic material on the dielectric layer, wherein the metallic material has a substantially planar top surface extends across the plurality of lower electrodes and fills in and between the U-shaped profile of the plurality of lower electrodes;

disposing a passivation layer on top surface of the metallic material; and

performing an alloy layer formation process to dispose a SiGe layer across top surface of the passivation layer;

wherein the SiGe layer has a Ge concentration distribution that has a greatest value at a middle portion of the SiGe layer and decreases there-from upwardly and downwardly along a thickness direction.

2. The method of claim 1 , wherein the performing the alloy layer formation process comprises supplying, in a cycle period, silane-based gas and germanium-based gas over the passivation layer, wherein a flow rate ratio between silane-based gas and germanium-based gas is raised and then reduced during the cycle period.

3. The method of claim 2 , wherein the cycle period includes an initial session, an intermediate session and a final session;

wherein, in the initial session, the flow rate ratio is set in a range from about 10% to 30%;

wherein, in the intermediate session, the flow rate ratio is set in a range from about 20 30% to 90%; and

wherein in the final session, the flow rate ratio is set in a range from about 10% to 30%.

4. The method of claim 3 , wherein a duration length ratio between the intermediate session and the initial session has a range of about 2 to about 3.

5. The method of claim 4 , wherein a duration length ratio between the intermediate session and the final session has a range of about 2 to about 3.

6. The method of claim 5 , further comprising performing a plurality of the alloy layer formation process to form a plurality of the SiGe layers stacked over the passivation layer.

7. The method of claim 6 , wherein a thickness of the stacked SiGe layers is in a range from about 1200 to about 1600 Å.

8. The method of claim 7 , wherein a thickness of the middle portion of each of the SiGe layer is in a range from about 100 to about 200 Å.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 20, 2020
From: CHOI, KEEWOUNG; LEE, HASUNG; KIM, SUNG-KI
To: XIA TAI XIN SEMICONDUCTOR (QING DAO) LTD.
Reel/Frame 052717/0832 →
Continuity (3)
Provisional Application 62781617 · Dec 19, 2018
Provisional Application 62779512 · Dec 14, 2018
Related Publication 20200219887A1 · Jul 9, 2020