Non-planar field effect transistor devices with low-resistance metallic gate structures
Methods are provided to construct field-effect transistors comprising low-resistance metallic gate structures. A field-effect transistor includes a nanosheet stack and a metal gate which covers a gate region of the nanosheet stack. The nanosheet stack includes nanosheet channel layers and an etch stop layer disposed above an upper nanosheet channel layer. The metal gate includes a work function metal which encapsulates the nanosheet channel layers, and a gate electrode disposed above and in contact with the work function metal. An upper surface of the work function metal is recessed to be substantially coplanar with the etch stop layer. The gate electrode has a resistivity which is less than a resistivity of the work function metal. The etch stop layer protects the portion of the work function metal disposed between the etch stop layer and the upper nanosheet channel layer from being etched when recessing the work function metal.
1. A semiconductor device, comprising:
a nanosheet stack structure disposed on a semiconductor substrate, wherein the nanosheet stack structure comprises active nanosheet channel layers and an etch stop layer disposed above an uppermost active nanosheet layer of the nanosheet stack structure; and
a metal gate structure covering the nanosheet stack structure, wherein the metal gate structure comprises:
a conformal layer of gate dielectric material disposed on surfaces of the etch stop layer and the active nanosheet channel layers;
a layer of work function metal which encapsulates the active nanosheet channel layers and fills spaces above and below each of the active nanosheet channel layers, wherein a size of the spaces above and below each of the active nanosheet channel layers is substantially the same, and wherein an upper surface of the layer of work function metal is disposed below an upper surface of the etch stop layer; and
a gate electrode disposed above the upper surface of the etch stop layer and above the upper surface of the layer of the work function metal and in contact with the upper surface of the layer of work function metal, wherein the gate electrode comprises a metallic material having a resistivity which is less than a resistivity of the work function metal.
2. The semiconductor device of claim 1 , wherein the etch stop layer comprises a dielectric material which has etch selectivity with respect to the gate dielectric material.
3. The semiconductor device of claim 1 , wherein the etch stop layer comprises a silicon-carbon-oxide material.
4. The semiconductor device of claim 1 , wherein the metallic material of the gate electrode comprises cobalt.
5. The semiconductor device of claim 1 , wherein the metallic material of the gate electrode comprises tungsten.
6. The semiconductor device of claim 1 , wherein the metallic material of the gate electrode comprises ruthenium.
7. The semiconductor device of claim 1 , further comprising:
a gate sidewall spacer disposed on sidewalls of the gate electrode;
a gate capping layer disposed above a recessed surface of the gate electrode; and
vertical source/drain contacts disposed adjacent to the gate sidewall spacer.
8. The semiconductor device of claim 1 , further comprising air spacers disposed adjacent to vertical sidewalls of the gate electrode.
9. The semiconductor device of claim 1 , wherein a thickness of the active nanosheet channel layers is in a range of about 6 nm to about 8 nm, and wherein a thickness of the etch stop layer is in a range of about 5 nm to about 7 nm.
10. The semiconductor device of claim 1 , wherein the gate dielectric material comprises a high-k dielectric material, wherein k is greater than 3.9.
11. The semiconductor device of claim 1 , wherein the active nanosheet channel layers are formed of epitaxial silicon.
12. The semiconductor device of claim 1 , wherein the active nanosheet channel layers are formed of an epitaxial silicon-germanium alloy.
13. A semiconductor device, comprising:
a nanosheet stack structure disposed on a semiconductor substrate, wherein the nanosheet stack structure comprises active nanosheet channel layers; and
a metal gate structure covering the nanosheet stack structure, wherein the metal gate structure comprises:
a conformal layer of gate dielectric material disposed on surfaces of the active nanosheet channel layers;
a layer of work function metal which encapsulates the active nanosheet channel layers and fills regions above and below each of the active nanosheet channel layers, wherein an upper surface of the layer of work function metal is disposed above an uppermost active nanosheet channel layer, and wherein a thickness of the work function metal in the regions above and below each of the active nanosheet channel layers is substantially the same; and
a gate electrode disposed above the upper surface of the layer of work function metal and in contact with the upper surface of the layer of work function metal, wherein the gate electrode comprises a metallic material having a resistivity which is less than a resistivity of the work function metal.
14. The semiconductor device of claim 13 , wherein the metallic material of the gate electrode comprises one of cobalt, tungsten, and ruthenium.
15. The semiconductor device of claim 13 , further comprising:
a gate sidewall spacer disposed on sidewalls of the gate electrode;
a gate capping layer disposed above a recessed surface of the gate electrode; and
vertical source/drain contacts disposed adjacent to the gate sidewall spacer.
16. The semiconductor device of claim 13 , further comprising air spacers disposed adjacent to vertical sidewalls of the gate electrode.
17. The semiconductor device of claim 13 , wherein the gate dielectric material comprises a high-k dielectric material, wherein k is greater than 3.9.
18. The semiconductor device of claim 13 , wherein the active nanosheet channel layers are formed of one of epitaxial silicon and a silicon-germanium alloy.
19. A semiconductor device, comprising:
a nanosheet stack structure disposed on a semiconductor substrate, wherein the nanosheet stack structure comprises active nanosheet channel layers and an etch stop layer disposed above an uppermost active nanosheet layer of the nanosheet stack structure; and
a metal gate structure covering the nanosheet stack structure, wherein the metal gate structure comprises:
a conformal layer of gate dielectric material disposed on surfaces of the etch stop layer and the active nanosheet channel layers;
a layer of work function metal which encapsulates the active nanosheet channel layers and fills spaces above and below each of the active nanosheet channel layers, wherein a size of the spaces above and below each of the active nanosheet channel layers is substantially the same, and wherein an upper surface of the layer of work function metal is substantially coplanar with an upper surface of the etch stop layer; and
a gate electrode disposed above the upper surface of the etch stop layer and above the upper surface of the layer of the work function metal and in contact with the upper surface of the layer of work function metal, wherein the gate electrode comprises a metallic material having a resistivity which is less than a resistivity of the work function metal.
20. The semiconductor device of claim 19 , wherein the metallic material of the gate electrode comprises one of cobalt, tungsten, and ruthenium.