Semiconductor device including an adder
View Patent ↗According to the embodiments, a semiconductor device includes: an adder configured to generate positive multiple data of the multiplicand which is used for a plurality of the multiplication in plurality and does not include a value of 2 n (n is a positive integer) of the multiplicand; a Wallace tree circuit provided in each of the multiplier circuits and configured to operate a sum of a plurality of partial products by using a plurality of adders; and a selection circuit provided in each of the multiplier circuits and configured to select, according to a plurality of bits selected from the multiplier, data falling in a multiple of one of the multiplicand, data of 2 n of the multiplicand, and the positive multiple data from the adder in order to output as one partial product of the plurality of partial products to the Wallace tree circuit.
1. A semiconductor device comprising:
a plurality of multiplier circuits each configured to perform multiplication by multiplying a binary multiplicand by a binary multiplier;
a first adder configured to generate positive multiple data of the multiplicand which is used for the multiplication and does not include a value of 2 n (n is a positive integer) of the multiplicand;
a register configured to store the positive multiple data;
a partial product adder circuit provided in each of the multiplier circuits and configured to operate a sum of a plurality of partial products by using a plurality of second adders; and
a selection circuit provided in each of the multiplier circuits and configured to select, according to a plurality of bits selected from the multiplier, data of a multiple of one of the multiplicand, data of 2 n of the multiplicand, and the positive multiple data in order to output as one partial product of the plurality of partial products to the partial product adder circuit, wherein
a clock signal applied to the register is suspended while a plurality of the multiplications are performed in a state where a value of the multiplicand remains unchanged.
2. The semiconductor device according to claim 1 , wherein each of the plurality of multiplier circuits includes a circuit configured to generate a value of 2 n of the multiplicand.
3. The semiconductor device according to claim 2 , wherein the circuit configured to generate a value of 2 n of the multiplicand is a shift circuit.
4. The semiconductor device according to claim 1 , wherein the partial product adder circuit is a Wallace tree circuit including the plurality of second adders arranged in a tree shape.
5. A semiconductor device, comprising:
a multiplier circuit configured to perform multiplication by niultiplyjim a binary multiplicand by a binary multiplier:
a first adder configured to generate positive multiple data of the multiplicand which is used for the multiplication and does not include a value of 2 n (n is a positive integer) of the multiplicand:
a register configured to store the positive multiple data, and
a partial product adder circuit provided in the multiplier circuit and configured to operate a sum of a plurality of partial products by using a plurality of second adders, wherein
the multiplier circuit outputs a plurality of products according to the multiplier selected at different timings based on a selection signal, and
a clock signal applied to the register is suspended while the one multiplier circuit calculates the plurality of products.
6. The semiconductor device according to claim 5 , wherein the partial product adder circuit is a Wallace tree circuit including the plurality of second adders arranged in a tree shape.