Threshold voltage adjustment for a gate-all-around semiconductor structure
A semiconductor structure includes a plurality of first semiconductor layers interleaved with a plurality of second semiconductor layers. The first and second semiconductor layers have different material compositions. A dummy gate stack is formed over an uppermost first semiconductor layer. A first etching process is performed to remove portions of the second semiconductor layer that are not disposed below the dummy gate stack, thereby forming a plurality of voids. The first etching process has an etching selectivity between the first semiconductor layer and the second semiconductor layer. Thereafter, a second etching process is performed to enlarge the voids.
1. A device, comprising:
a first nanostructure and a second nanostructure each having an elongated shape, wherein the first nanostructure and the second nanostructure each contain a semiconductive material;
a first gate located at least above or below the first nanostructure in a cross-sectional view;
a second gate located at least above or below the second nanostructure in the cross-sectional view, wherein the first gate and the second gate have different sizes;
a source/drain region located between the first gate and the second gate;
wherein:
the first nanostructure and the second nanostructure are connected by a third nanostructure that is located directly above or below the source/drain region in the cross-sectional view; and
the first nanostructure and the third nanostructure have different thicknesses.
2. The device of claim 1 , wherein the first gate at least partially wraps around the first nanostructure, and wherein the second gate at least partially wraps around the second nanostructure.
3. The device of claim 1 , further including:
a third nanostructure located above or below the first nanostructure in the cross-sectional view; and
a fourth nanostructure located above or below the second nanostructure in the cross-sectional view.
4. The device of claim 1 , wherein:
the first nanostructure and the second nanostructure each extend in a first direction; and
the first gate and the second gate have different sizes in the first direction.
5. The device of claim 4 , wherein:
the first gate corresponds to a first transistor with a first threshold voltage;
the second gate corresponds to a second transistor with a first threshold voltage that is greater than the first threshold voltage; and
the second gate is longer than the first gate in the first direction.
6. The device of claim 5 , wherein the second gate is about 1.5 to about 2 times longer than the first gate in the first direction.
7. The device of claim 1 , wherein the first gate and the second gate each includes:
a gate dielectric having a dielectric constant greater than a dielectric constant of silicon oxide; and
a metal gate electrode.
8. The device of claim 1 , wherein:
the first gate circumferentially surrounds at least a portion of the first nanostructure; and
the second gate circumferentially surrounds at least a portion of the second nanostructure.
9. A device, comprising:
a nanostructure that includes a first portion, a second portion, and a third portion that each extend in a first direction, wherein the third portion is disposed between the first portion and the second portion, wherein the first portion corresponds to a first semiconductor channel, and wherein the second portion corresponds to a second semiconductor channel;
a first gate that at least partially wraps around the first semiconductor channel;
a second gate that at least partially wraps around the second semiconductor channel; and
a source/drain located between the first gate and the second gate and above or below the third portion of the nanostructure in a cross-sectional view;
wherein:
the first gate and the second gate have different lengths in the first direction;
the first gate and the second gate belong to a first transistor and a second transistor, respectively; and
the first transistor and the second transistor are configured to have different amounts of threshold voltages.
10. The device of claim 9 , wherein:
the second gate is longer than the first gate in the first direction; and
the second transistor is configured to have a greater threshold voltage than the first transistor.
11. The device of claim 10 , wherein the second gate is longer than the first gate in the first direction by about 1.5 times to about 2 times.
12. The device of claim 9 , wherein the nanostructure is a first nanostructure, wherein the device further includes a plurality of additional nanostructures that are vertically stacked above or below the first nanostructure in the cross-sectional view.
13. The device of claim 9 , wherein the third portion has a different thickness than the first portion or the second portion of the nanostructure.
14. The device of claim 9 , wherein:
the first gate circumferentially wraps around a portion of the first semiconductor channel; and
the second gate circumferentially wraps around a portion of the second semiconductor channel.
15. The device of claim 9 , wherein the source/drain is located above or below the third portion of the nanostructure in a second direction perpendicular to the first direction.
16. A device, comprising:
a plurality of first semiconductor nanostructures that each extends in a first direction, wherein the first semiconductor nanostructures are vertically stacked over one another in a second direction different from the first direction;
a plurality of second semiconductor nanostructures that each extends in the first direction, wherein the second semiconductor nanostructures are vertically stacked over one another in the second direction;
a plurality of first gates that each at least partially circumferentially surrounds at least one of the first semiconductor nanostructures;
a plurality of second gates that each at least partially circumferentially surrounds at least one of the second semiconductor nanostructures;
a plurality of source/drain components disposed between the first gates and the second gates in the first direction; and
a plurality of third semiconductor nanostructures, wherein the source/drain components interleave with the third semiconductor nanostructures in the second direction;
wherein the third semiconductor nanostructures have different thicknesses than the first semiconductor nanostructures or the second semiconductor nanostructures, and wherein the thicknesses are measured in a third direction different from the first direction and the second direction.
17. The device of claim 16 , wherein:
the first gates correspond to one or more first transistors configured to have a first threshold voltage; and
the second gates correspond to one or more second transistors having a second threshold voltage greater than the first threshold voltage.
18. The device of claim 16 , wherein each of the second gates is longer than each of the first gates in the first direction.
19. The device of claim 18 , wherein the third semiconductor nanostructures are thinner than the first semiconductor nanostructures or the second semiconductor nanostructures.
20. The device of claim 16 , wherein each of the second gates is about 1.5 to about 2 times longer than each of the first gates in the first direction.