Providing multi-element multi-vector (MEMV) register file access in vector-processor-based devices
Providing multi-element multi-vector (MEMV) register file access in vector-processor-based devices is disclosed. In this regard, a vector-processor-based device includes a vector processor comprising multiple processing elements (PEs) communicatively coupled via a corresponding plurality of channels to a vector register file comprising a plurality of memory banks. The vector processor provides a direct memory access (DMA) controller that is configured to receive a plurality of vectors that each comprise a plurality of vector elements representing operands for processing a loop iteration. The DMA controller arranges the vectors in the vector register file such that, for each group of vectors to be accessed in parallel, vector elements for each vector are stored consecutively, but corresponding vector elements of consecutive vectors are stored in different memory banks of the vector register file. As a result, multiple elements of multiple vectors may be accessed with a single vector register file access operation.
1. A vector-processor-based device for providing multi-element multi-vector (MEMV) register file access, comprising:
a plurality of processing elements (PEs);
a vector register file comprising a plurality of memory banks and communicatively coupled to the plurality of PEs via a corresponding plurality of channels; and
a direct memory access (DMA) controller configured to:
receive a plurality of vectors, each comprising a plurality of vector elements; and
write the plurality of vectors into the vector register file such that, for each group of vectors of the plurality of vectors to be accessed in parallel, corresponding vector elements belonging to different vectors within the group of vectors are stored in different memory banks of the plurality of memory banks of the vector register file.
2. The vector-processor-based device of claim 1 , wherein each PE of the plurality of PEs comprises a plurality of constituent PEs configured to function as a single fused PE.
3. The vector-processor-based device of claim 1 , wherein the DMA controller is configured to write the plurality of vectors into the vector register file by being configured to:
left-align a first vector of each group of vectors within the vector register file; and
offset the plurality of vector elements of each subsequent vector of the group of vectors by a number of memory banks of the plurality of memory banks equal to a number of PEs of the plurality of PEs, relative to a previous vector of the group of vectors.
4. The vector-processor-based device of claim 1 , wherein a size of each group of vectors of the plurality of vectors to be accessed in parallel is determined by a ratio of total bandwidth of the plurality of channels, and a product of a total number of PEs of the plurality of PEs and a computational precision.
5. The vector-processor-based device of claim 1 , further comprising a programmable placement table comprising a plurality of placement table entries, wherein:
each placement table entry of the plurality of placement table entries comprises a loop identifier representing a loop, a PE indicator representing a number of PEs for processing the loop, and a computational precision indicator for processing the loop; and
the DMA controller is configured to write the plurality of vectors into the vector register file based on a placement table entry of the plurality of placement table entries of the programmable placement table corresponding to the loop.
6. The vector-processor-based device of claim 5 , wherein the DMA controller is further configured to:
read a plurality of vector elements of each vector of the group of vectors from the vector register file based on the programmable placement table; and
provide the plurality of vector elements to the plurality of PEs for processing of the loop.
7. The vector-processor-based device of claim 5 , further comprising a crossbar switch configured to:
receive execution results from the plurality of PEs; and
write the execution results to the vector register file based on the programmable placement table.
8. The vector-processor-based device of claim 1 integrated into an integrated circuit (IC).
9. The vector-processor-based device of claim 1 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter.
10. A vector-processor-based device for handling branch divergence in loops, comprising:
a means for receiving a plurality of vectors, each comprising a plurality of vector elements; and
a means for writing the plurality of vectors into a vector register file comprising a plurality of memory banks and communicatively coupled to a plurality of processing elements (PEs) via a corresponding plurality of channels, such that, for each group of vectors of the plurality of vectors to be accessed in parallel, corresponding vector elements belonging to different vectors within the group of vectors are stored in different memory banks of the plurality of memory banks of the vector register file.
11. A method for providing multi-element multi-vector (MEMV) register file access, comprising:
receiving, by a direct memory access (DMA) controller of a vector-processor-based device, a plurality of vectors, each comprising a plurality of vector elements; and
writing the plurality of vectors into a vector register file comprising a plurality of memory banks and communicatively coupled to a plurality of processing elements (PEs) via a corresponding plurality of channels, such that, for each group of vectors of the plurality of vectors to be accessed in parallel, corresponding vector elements belonging to different vectors within the group of vectors are stored in different memory banks of the plurality of memory banks of the vector register file.
12. The method of claim 11 , wherein each PE of the plurality of PEs comprises a plurality of constituent PEs configured to function as a single fused PE.
13. The method of claim 11 , wherein writing the plurality of vectors into the vector register file comprises:
left-aligning a first vector of each group of vectors within the vector register file; and
offsetting the plurality of vector elements of each subsequent vector of the group of vectors by a number of memory banks of the plurality of memory banks equal to a number of PEs of the plurality of PEs, relative to a previous vector of the group of vectors.
14. The method of claim 11 , wherein a size of each group of vectors of the plurality of vectors to be accessed in parallel is determined by a ratio of total bandwidth of the plurality of channels, and a product of a total number of PEs of the plurality of PEs and a computational precision.
15. The method of claim 11 , further comprising writing the plurality of vectors into the vector register file based on a placement table entry of a plurality of placement table entries of a programmable placement table corresponding to a loop;
wherein each placement table entry of the plurality of placement table entries comprises a loop identifier representing the loop, a PE indicator representing a number of PEs for processing the loop, and a computational precision indicator for processing the loop.
16. The method of claim 15 , further comprising:
reading, by the DMA controller, a plurality of vector elements of each vector of the group of vectors from the vector register file based on the programmable placement table; and
providing the plurality of vector elements to the plurality of PEs for processing of the loop.
17. The method of claim 15 , further comprising:
receiving, by a crossbar switch of the vector-processor-based device, execution results from the plurality of PEs; and
writing the execution results to the vector register file based on the programmable placement table.
18. A non-transitory computer-readable medium, having stored thereon computer-executable instructions for causing a vector processor of a vector-processor-based device to:
receive a plurality of vectors, each comprising a plurality of vector elements; and
write the plurality of vectors into a vector register file comprising a plurality of memory banks and communicatively coupled to a plurality of processing elements (PEs) via a corresponding plurality of channels, such that, for each group of vectors of the plurality of vectors to be accessed in parallel, corresponding vector elements belonging to different vectors within the group of vectors are stored in different memory banks of the plurality of memory banks of the vector register file.
19. The non-transitory computer-readable medium of claim 18 , wherein each PE of the plurality of PEs comprises a plurality of constituent PEs configured to function as a single fused PE.
20. The non-transitory computer-readable medium of claim 18 , wherein the computer-executable instructions for causing the vector processor to write the plurality of vectors into the vector register file comprise computer-executable instructions for causing the vector processor to:
left-align a first vector of each group of vectors within the vector register file; and
offset the plurality of vector elements of each subsequent vector of the group of vectors by a number of memory banks of the plurality of memory banks equal to a number of PEs of the plurality of PEs, relative to a previous vector of the group of vectors.
21. The non-transitory computer-readable medium of claim 18 , wherein a size of each group of vectors of the plurality of vectors to be accessed in parallel is determined by a ratio of total bandwidth of the plurality of channels, and a product of a total number of PEs of the plurality of PEs and a computational precision.
22. The non-transitory computer-readable medium of claim 18 having stored thereon computer-executable instructions for further causing the vector processor to write the plurality of vectors into the vector register file based on a placement table entry of a plurality of placement table entries of a programmable placement table corresponding to a loop;
wherein each placement table entry of the plurality of placement table entries comprises a loop identifier representing the loop, a PE indicator representing a number of PEs for processing the loop, and a computational precision indicator for processing the loop.
23. The non-transitory computer-readable medium of claim 22 having stored thereon computer-executable instructions for further causing the vector processor to:
read a plurality of vector elements of each vector of the group of vectors from the vector register file based on the programmable placement table; and
provide the plurality of vector elements to the plurality of PEs for processing of the loop.
24. The non-transitory computer-readable medium of claim 22 having stored thereon computer-executable instructions for further causing the vector processor to:
receive execution results from the plurality of PEs; and
write the execution results to the vector register file based on the programmable placement table.