Memory module and system supporting parallel and serial access modes
A memory module can be programmed to deliver relatively wide, low-latency data in a first access mode, or to sacrifice some latency in return for a narrower data width, a narrower command width, or both, in a second access mode. The narrow, higher-latency mode requires fewer connections and traces. A controller can therefore support more modules, and thus increased system capacity. Programmable modules thus allow computer manufacturers to strike a desired balance between memory latency, capacity, and cost.
1. A memory module supporting a serial-access mode and a parallel-access mode, the memory module comprising:
a module connector to communicate data, commands, and addresses;
an integrated-circuit (IC) memory device to store the data and communicate the stored data in parallel as parallel read data;
a memory-buffer IC having:
a memory-device data interface coupled to the memory device to communicate the parallel read data;
a serial controller data interface, of a first data width, to serialize the parallel read data and communicate the serialized read data to the module connector; and
a parallel controller data interface, of a second data width greater than the first data width, to communicate the parallel read data to the module connector; and
a command-and-address (CA) buffer IC coupled to the module connector, the IC memory device, and the memory-buffer IC, CA buffer to manage the flow of the read data from the IC memory device and through the memory-buffer IC to the module connector responsive to the commands and addresses.
2. The memory module of claim 1 , further comprising data lines extending from the serial controller data interface to the module connector.
3. The memory module of claim 2 , the data lines further extending from the parallel controller data interface.
4. The memory module of claim 1 , wherein the serial controller data interface communicates the serialized read data as a differential signal.
5. The memory module of claim 4 , wherein the parallel controller data interface communicates the data as single-ended signals.
6. The memory module of claim 1 , the memory-buffer IC further having a mode register to select between the serial controller data interface and the parallel controller data interface.
7. The memory module of claim 6 , the memory-buffer IC further having a command decoder coupled to the mode register, the command decoder to load the mode register responsive to a mode command.