Display panel and method of manufacturing same, and display module

1. A display panel, comprising:

a substrate; and

a scanning signal wire layer disposed on the substrate, wherein the scanning signal wire layer comprises a gate electrode layer and a source/drain electrode layer;

wherein the gate electrode layer comprises a gate electrode and a scanning signal wire;

wherein the source/drain electrode layer comprises a source electrode, a drain electrode, and a power drive wire;

wherein the display panel further comprises at least one resistance-reduction wire disposed between the substrate and the source/drain electrode layer, and a shading layer; and

wherein the at least one resistance-reduction wire is electrically connected to the power drive wire by a through hole and comprises a first resistance reduction wire;

wherein the first resistance-reduction wire is electrically connected to the power drive wire by a first through hole and is parallel to the scanning signal wire, the shading layer is disposed between the substrate and the gate electrode layer, and the first resistance-reduction wire is disposed on a same layer as the shading layer.

2. The display panel of claim 1 , wherein the first resistance-reduction wire is disposed on a same layer as the scanning signal wire.

3. The display panel of claim 1 , wherein the scanning signal wire layer comprises:

a first gate electrode layer comprising at least one first gate electrode and a scanning signal wire;

a second gate electrode layer disposed on the first gate electrode layer; wherein the second gate electrode layer comprises at least one second gate electrode disposed corresponding to the first gate electrode;

wherein the first gate electrode and the second gate electrode form a storage capacitor; and

wherein the first resistance-reduction wire is disposed on a same layer as the second gate electrode.

4. The display panel of claim 3 , wherein the second gate electrode layer further comprises a reset signal wire;

wherein the reset signal wire is parallel to the scanning signal wire; and

wherein the first resistance-reduction wire is disposed between edge lines of two adjacent pixel units and the reset signal wire.

5. The display panel of claim 1 , wherein the display panel further comprises a second resistance-reduction wire;

wherein the first resistance-reduction wire is disposed on a same layer as one of a shading layer, a first gate electrode layer, and a second gate electrode layer;

wherein the second resistance-reduction wire is disposed on a same layer as one of the shading layer, the first gate electrode layer, and the second gate electrode layer;

wherein the first resistance-reduction wire and the second resistance-reduction wire are disposed on different layers; and

wherein the second resistance-reduction wire is electrically connected to the power drive wire by a second through hole.

6. The display panel of claim 5 , wherein the display panel further comprises a third resistance-reduction wire;

wherein the third resistance-reduction wire is disposed on a same layer as one of the shading layer, the first gate electrode layer, and the second gate electrode layer;

wherein the first resistance-reduction wire, the second resistance-reduction wire, and the third resistance-reduction wire are disposed on different layers; and

wherein the third resistance-reduction wire is electrically connected to the power drive wire by a third through hole.

7. A method of manufacturing a display panel, comprising a plurality of steps of:

step 10 : providing a substrate;

step 20 : disposing a first metal layer on the substrate, and patterning the first metal layer to form a gate electrode and a scanning signal wire; and

step 30 : disposing a third metal layer on the first metal layer, and patterning the third metal layer to form a source electrode, a drain electrode, and a power drive wire;

wherein the method further comprises a step of:

disposing at least one resistance-reduction wire between the substrate and the third metal layer;

wherein the at least one resistance-reduction wire is electrically connected to the power drive wire by a through hole and comprises a first resistance-reduction wire;

wherein the first resistance-reduction wire is electrically connected to the power drive wire by a first through hole and is parallel to the scanning signal wire; and

wherein a fourth metal layer is disposed on the substrate to form a shading layer and the first resistance-reduction wire by a patterning process before the step of disposing a first metal layer on the substrate.

8. The method of claim 7 , wherein the step 20 comprises a plurality of steps of:

step 201 : disposing the first metal layer on the substrate; and

step 202 : patterning the first metal layer to form at least one first gate electrode, the scanning signal wire, and the first resistance-reduction wire.

9. The method of claim 8 , wherein the step 20 comprises a plurality of steps of:

step 211 : disposing the first metal layer on the substrate;

step 212 : patterning the first metal layer to form at least one first gate electrode and the scanning signal wire;

step 213 : disposing a second metal layer on the first metal layer; and

step 214 : patterning the second metal layer to form at least one second gate electrode and the first resistance-reduction wire;

wherein the first gate electrode and the second gate electrode are disposed corresponding to each other; and

wherein the first gate electrode and the second gate electrode form a storage capacitor.

10. The method of claim 9 , wherein the step 214 comprises a step of:

patterning the second metal layer to form at least one second gate electrode, the first resistance-reduction wire, and a reset signal wire;

wherein the reset signal wire is parallel to the scanning signal wire; and

wherein the first resistance-reduction wire is disposed between edge lines of two adjacent pixel units and the reset signal wire.

11. The method of claim 7 , wherein the step of disposing at least one resistance-reduction wire between the substrate and the third metal layer comprises a plurality of steps of:

disposing the first resistance-reduction wire on the substrate; and

disposing a second resistance-reduction wire on the first resistance-reduction wire;

wherein the first resistance-reduction wire is disposed on a same layer as a shading layer, and the second resistance-reduction wire is disposed on a same layer as a first gate electrode layer or a second gate electrode layer; or

wherein the first resistance-reduction wire is disposed on a same layer as the first gate electrode layer, and the second resistance-reduction wire is disposed on a same layer as the second gate electrode layer; and

wherein the first resistance-reduction wire is electrically connected to the power drive wire by a first through hole, and the second resistance-reduction wire is electrically connected to the power drive wire by a second through hole.

12. The method of claim 7 , wherein the step of disposing at least one resistance-reduction wire between the substrate and the third metal layer comprises a plurality of steps of:

disposing the first resistance-reduction wire on the substrate;

disposing a second resistance-reduction wire on the first resistance-reduction wire; and

disposing a third resistance-reduction wire on the second resistance-reduction wire;

wherein the first resistance-reduction wire is disposed on a same layer as a shading layer, the second resistance-reduction wire is disposed on a same layer as a first gate electrode layer, and the second resistance-reduction wire is disposed on a same layer as a second gate electrode layer.

13. A display module, comprising:

a display panel; and

a polarizing layer and a cover layer disposed on the display panel;

wherein the display panel comprises a substrate, and a scanning signal wire layer disposed on the substrate;

wherein the scanning signal wire layer comprises a gate electrode layer and a source/drain electrode layer;

wherein the gate electrode layer comprises a gate electrode and a scanning signal wire;

wherein the source/drain electrode layer comprises a source electrode, a drain electrode, and a power drive wire; and

wherein at least one resistance-reduction wire is electrically connected to the power drive wire by a through hole and comprises a first resistance-reduction wire and a second resistance-reduction wire;

wherein the first resistance-reduction wire is electrically connected to the power drive wire by a first through hole, and the first resistance-reduction wire is parallel to the scanning signal wire;

wherein the first resistance-reduction wire is disposed on a same layer as one of a shading layer, a first gate electrode layer, and a second gate electrode layer;

wherein the second resistance-reduction wire is disposed on a same layer as one of the shading layer, the first gate electrode layer, and the second gate electrode layer;

wherein the first resistance-reduction wire and the second resistance-reduction wire are disposed on different layers; and

wherein the second resistance-reduction wire is electrically connected to the power drive wire by a second through hole.

14. The display module of claim 13 , wherein the display panel further comprises a third resistance-reduction wire;

wherein the third resistance-reduction wire is disposed on a same layer as one of the shading layer, the first gate electrode layer, and the second gate electrode layer;

wherein the first resistance-reduction wire, the second resistance-reduction wire, and the third resistance-reduction wire are disposed on different layers; and

wherein the third resistance-reduction wire is electrically connected to the power drive wire by a third through hole.