IP Library Granted Patent US 11,049,962
Granted Patent B2
US 11,049,962 · App. 16/741,800 · Granted Jun 29, 2021

Silicon carbide power devices

Inventors: Siddarth Sundaresan (Dulles, VA); Ranbir Singh (Dulles, VA); Jaehoon Park (Dulles, VA)
Assignee: GeneSiC Semiconductor Inc.
H01L29/7802H01L29/0865H01L29/1608
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Quick Facts
Patent No.
US 11,049,962
App. No.
16/741,800
Granted
Jun 29, 2021
Kind
B2
Abstract

An embodiment relates to a device comprising a unit cell on a SiC substrate, the unit cell comprising a gate insulator film, a trench in the well region, and a first sinker region of a second conduction type, wherein the first sinker region has a depth that is equal to or greater than a depth of a well region; wherein the device has an on-resistance of less than 3 milliohm-cm 2 , a gate threshold voltage of greater than 2.8V, a breakdown voltage of greater than 1450V, and an electric field of less than 3.5 megavolt/cm in the gate insulator film at a drain voltage of less than or equal to 1200 V.

Claims (37)

1. A device comprising a unit cell on a SiC substrate, the unit cell comprising:

a gate insulator film,

a trench in a well region,

a first sinker region having a second conduction type, wherein the first sinker region has a depth that is equal to or greater than a depth of the well region, and

a second sinker region having the second conduction type;

wherein each of the first sinker region and the second sinker region is in contact with a region having a first conduction type to form a p-n junction.

2. The device of claim 1 , wherein the device comprises a semiconductor metal-insulator-semiconductor transistor component.

3. The device of claim 1 , wherein the well region is next to an insulator-semiconductor interface; and a source region of the first conduction type formed within the well region.

4. The device of claim 3 , wherein a depth of the trench is greater than or equal to a thickness of the source region.

5. The device of claim 1 , wherein the first sinker region is located below the trench.

6. The device of claim 1 , wherein a depth of the second sinker region is less than a depth of the first sinker region.

7. The device of claim 1 , wherein a depth of the second sinker region is greater than a depth of the well region.

8. The device of claim 1 , wherein the device has an on-resistance of less than 4 milliohm centimeter squared, a gate threshold voltage of greater than 1.5 Volt, a breakdown voltage of greater than 500 Volt, and an electric field of less than 3.5 megavolt per cm in the gate insulator film.

9. A device comprising a unit cell on a SiC substrate, the unit cell comprising:

a gate insulator film,

a trench in a well region,

a first sinker region of a second conduction type,

a second sinker region of the second conduction type, and

a source region;

wherein the source region is in direct contact with the second sinker region.

10. The device of claim 9 , wherein the device comprises a semiconductor metal-insulator-transistor component.

11. The device of claim 9 , wherein the unit cell further comprises a semiconductor body of a first conduction type that comprises a drift zone; the well region of the second conduction type next to an insulator-semiconductor interface; and a source region of the first conduction type formed within the well region.

12. The device of claim 11 , wherein a depth of the trench is greater than or equal to a thickness of the source region.

13. The device of claim 9 , wherein a depth of the trench is greater than a depth of the source region.

14. The device of claim 9 , wherein the device has an avalanche energy of greater than 10 Joule per centimeter squared, calculated by dividing an avalanche energy in Joules by a total die area in centimeter squared.

15. The device of claim 9 , wherein an avalanche failure is located within the unit cell.

16. A device comprising a unit cell on a SiC substrate, the unit cell comprising:

a gate insulator film,

a trench in a well region,

a first sinker region of a second conduction type,

a second sinker region of the second conduction type, and

a source region;

wherein the first sinker region has a depth that is greater than a depth of the second sinker region;

wherein the second sinker has a width that is greater than that of the first sinker.

17. The device of claim 16 , wherein the first sinker region is located below the trench.

18. The device of claim 16 , wherein a depth of the second sinker region is less than a depth of the first sinker region.

19. The device of claim 16 , wherein a depth of the second sinker region is greater than a depth of the well region.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 14, 2020
From: SUNDARESAN, SIDDARTH; SINGH, RANBIR; PARK, JAEHOON
To: GENESIC SEMICONDUCTOR INC.
Reel/Frame 051503/0074 →
Continuity (2)
Continuation 16670963 · Oct 31, 2019
Related Publication 20210134998A1 · May 6, 2021