Method of erasing data in nonvolatile memory device, nonvolatile memory device performing the same and memory system including the same
View Patent ↗A nonvolatile memory device includes a memory cell region, a peripheral circuit region, a memory block in the memory cell region, a row decoder in the peripheral circuit region, and a control circuit in the peripheral circuit region. The memory cell region includes a first metal pad. The peripheral circuit region includes a second metal pad and is vertically connected to the memory cell region by the first metal pad and the second metal pad. The memory block includes memory cells stacked in a direction intersecting a substrate, and is divided into a plurality of sub-blocks configured to be erased independently. The row decoder selects the memory block by units of a sub-block. The control circuit receives a data erase command for a selected sub-block among the plurality of sub-blocks, performs a data read operation on at least one victim sub-block among the plurality of sub-blocks in response to the data erase command, selectively performs a soft program operation on the at least one victim sub-block based on a result of the data read operation, and performs a data erase operation on the selected sub-block after the data read operation is performed and the soft program operation is selectively performed.
1. A nonvolatile memory device comprising:
a memory cell region including a first metal pad;
a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad;
a memory block in the memory cell region including memory cells stacked in a direction intersecting a substrate, the memory block being divided into a plurality of sub-blocks configured to be erased independently;
a row decoder in the peripheral circuit region configured to select the memory block by units of a sub-block; and
a control circuit in the peripheral circuit region configured to receive a data erase command for a selected sub-block among the plurality of sub-blocks, to perform a data read operation on at least one victim sub-block among the plurality of sub-blocks in response to the data erase command, to selectively perform a soft program operation on the at least one victim sub-block based on a result of the data read operation, and to perform a data erase operation on the selected sub-block after the data read operation is performed and the soft program operation is selectively performed.
2. The nonvolatile memory device of claim 1 , wherein the data erase operation is performed by providing an erase voltage to a bulk region of a substrate on which the memory block extends; and wherein the at least one victim sub-block is disposed between the selected sub-block and the substrate.
3. The nonvolatile memory device of claim 1 , wherein the memory block comprises a common source line; and wherein the at least one victim sub-block extends closer to the common source line relative to the selected sub-block.
4. The nonvolatile memory device of claim 1 , wherein the data read operation is performed by reading first victim memory cells among a plurality of victim memory cells included in the at least one victim sub-block, using a first read voltage; and wherein the first victim memory cells are commonly connected to a first word line within the memory block.
5. The nonvolatile memory device of claim 4 , wherein the soft program operation is a one-shot program operation during which at least a plurality of the first victim memory cells are simultaneously programmed.
6. The nonvolatile memory device of claim 1 , wherein the soft program operation is a one-shot program operation during which at least a plurality of memory cells within the at least one victim sub-block are simultaneously programmed to thereby increase their respective threshold voltages.
7. The nonvolatile memory device of claim 1 , wherein the nonvolatile memory device is a three-dimensional memory device comprising a plurality of vertical NAND strings of nonvolatile memory cells.
8. The nonvolatile memory device of claim 1 , wherein the first metal pad and the second metal pad are formed of copper.
9. The nonvolatile memory device of claim 1 , wherein the first metal pad and the second metal pad are connected by bonding manner.
10. The nonvolatile memory device of claim 1 , wherein the memory cell region is formed on a first wafer and the peripheral circuit region is formed on a second wafer.