Updating corrective read voltage offsets in non-volatile random access memory

1. A computer-implemented method, comprising, for pages in a block of memory:

using a first calibration scheme to calibrate a given page in the block, wherein the first calibration scheme is configured to calculate a first number of independent read voltage offset values and a first number of common read voltage offset values for pages in a block of memory;

in response to determining that an error correction code failure occurred when attempting to read the calibrated given page, using a second calibration scheme to recalibrate the given page in the block, wherein the second calibration scheme is configured to calculate a second number of independent read voltage offset values and a second number of common read voltage offset values for pages in a block of memory;

and

in response to determining that an error correction code failure occurred when attempting to read the recalibrated given page, sending one or more instructions to relocate data stored in the given page.

2. The computer-implemented method of claim 1 , comprising:

in response to determining that an error correction code failure did not occur when attempting to read the calibrated given page, determining whether an error count corresponding to the given page is in a first predetermined range; and

in response to determining that the error count corresponding to the given page is in the first predetermined range, using the second calibration scheme to recalibrate the given page in the block.

3. The computer-implemented method of claim 1 , comprising:

in response to determining that an error correction code failure did not occur when attempting to read the recalibrated given page, determining whether an error count corresponding to the given page is in a second predetermined range; and

in response to determining that the error count corresponding to the given page is in the second predetermined range, sending one or more instructions to relocate data stored in the given page.

4. The computer-implemented method of claim 3 , comprising:

in response to determining that the error count corresponding to the given page is not in the second predetermined range, incrementing an error-recovery counter which corresponds to the given page;

determining whether the error-recovery counter corresponding to the given page is in a third predetermined range; and

in response to determining that the error-recovery counter corresponding to the given page is in the third predetermined range, sending one or more instructions to relocate data stored in the given page.

5. The computer-implemented method of claim 1 , wherein using the first calibration scheme to calibrate the given page in the block includes:

determining one or more read voltages associated with a page type that corresponds to the given page;

determining one or more existing read voltage offset values which correspond to the one or more read voltages;

computing a corrective offset for each of the existing read voltage offset values; and

using the corrective offsets to update the existing read voltage offset values.

6. The computer-implemented method of claim 5 , wherein the corrective offsets are used to update the existing read voltage offset values based on a first mapped relationship which extends between the corrective offsets and the existing read voltage offset values, wherein the first mapped relationship corresponds to the first calibration scheme.

7. The computer-implemented method of claim 1 , wherein using the second calibration scheme to calibrate the given page in the block includes:

determining one or more read voltages associated with a page type that corresponds to the given page;

determining one or more existing read voltage offset values which correspond to the one or more read voltages;

computing a corrective offset for each of the existing read voltage offset values; and

using the corrective offsets to update the existing read voltage offset values.

8. The computer-implemented method of claim 7 , wherein the corrective offsets are used to update the existing read voltage offset values based on a second mapped relationship which extends between the corrective offsets and the existing read voltage offset values, wherein the second mapped relationship corresponds to the second calibration scheme.

9. The computer-implemented method of claim 1 , wherein the memory is three-dimensional quad-level-cell NAND Flash, wherein the first number of independent read voltage offset values is less than the second number of independent read voltage offset values.

10. A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions readable and/or executable by a processor to cause the processor to, for pages in a block of memory:

use, by the processor, a first calibration scheme to calibrate a given page in the block, wherein the first calibration scheme is configured to calibrate a first number of independent read voltage offset values and a first number of common read voltage offset values for pages in a block of memory;

in response to determining that an error correction code failure occurred when attempting to read the calibrated given page, use, by the processor, a second calibration scheme to recalibrate the given page in the block, wherein the second calibration scheme is configured to calibrate a second number of independent read voltage offset values and a second number of common read voltage offset values for pages in a block of memory;

and

in response to determining that an error correction code failure occurred when attempting to read the recalibrated given page, send, by the processor, one or more instructions to relocate data stored in the given page.

11. The computer program product of claim 10 , wherein the program instructions are readable and/or executable by the processor to cause the processor to:

in response to determining that an error correction code failure did not occur when attempting to read the calibrated given page, determine, by the processor, whether an error count corresponding to the given page is in a first predetermined range; and

in response to determining that the error count corresponding to the given page is in the first predetermined range, use, by the processor, the second calibration scheme to recalibrate the given page in the block.

12. The computer program product of claim 10 , wherein the program instructions are readable and/or executable by the processor to cause the processor to:

in response to determining that an error correction code failure did not occur when attempting to read the recalibrated given page, determine, by the processor, whether an error count corresponding to the given page is in a second predetermined range; and

in response to determining that the error count corresponding to the given page is in the second predetermined range, send, by the processor, one or more instructions to relocate data stored in the given page.

13. The computer program product of claim 12 , wherein the program instructions are readable and/or executable by the processor to cause the processor to:

in response to determining that the error count corresponding to the given page is not in the second predetermined range, increment, by the processor, an error-recovery counter which corresponds to the given page;

determine, by the processor, whether the error-recovery counter corresponding to the given page is in a third predetermined range; and

in response to determining that the error-recovery counter corresponding to the given page is in the third predetermined range, send, by the processor, one or more instructions to relocate data stored in the given page.

14. The computer program product of claim 10 , wherein using the first calibration scheme to calibrate the given page in the block includes:

determining one or more read voltages associated with a page type that corresponds to the given page;

determining one or more existing read voltage offset values which correspond to the one or more read voltages;

computing a corrective offset for each of the existing read voltage offset values; and

using the corrective offsets to update the existing read voltage offset values.

15. The computer program product of claim 14 , wherein the corrective offsets are used to update the existing read voltage offset values based on a first mapped relationship which extends between the corrective offsets and the existing read voltage offset values, wherein the first mapped relationship corresponds to the first calibration scheme.

16. The computer program product of claim 10 , wherein using the second calibration scheme to calibrate the given page in the block includes:

determining one or more read voltages associated with a page type that corresponds to the given page;

determining one or more existing read voltage offset values which correspond to the one or more read voltages;

computing a corrective offset for each of the existing read voltage offset values; and

using the corrective offsets to update the existing read voltage offset values.

17. The computer program product of claim 16 , wherein the corrective offsets are used to update the existing read voltage offset values based on a second mapped relationship which extends between the corrective offsets and the existing read voltage offset values, wherein the second mapped relationship corresponds to the second calibration scheme.

18. The computer program product of claim 10 , wherein the memory is three-dimensional quad-level-cell NAND Flash, wherein the first number of independent read voltage offset values is less than the second number of independent read voltage offset values.

19. A system, comprising:

a plurality of non-volatile random access memory (NVRAM) blocks configured to store data;

a processor; and

logic integrated with and/or executable by the processor, the logic being configured to, for pages in one of the blocks:

use, by the processor, a first calibration scheme to calibrate a given page in the block, wherein the first calibration scheme is configured to calibrate a first number of independent read voltage offset values and a first number of common read voltages for pages in a block of memory;

in response to determining that an error correction code failure occurred when attempting to read the calibrated given page, use, by the processor, a second calibration scheme to recalibrate the given page in the block, wherein the second calibration scheme is configured to calibrate a second number of independent read voltage offset values and a second number of common read voltages for pages in a block of memory;

and

in response to determining that an error correction code failure occurred when attempting to read the recalibrated given page, send, by the processor, one or more instructions to relocate data stored in the given page.

20. The system of claim 19 , the logic being configured to:

in response to determining that an error correction code failure did not occur when attempting to read the calibrated given page, determine, by the processor, whether an error count corresponding to the given page is in a first predetermined range; and

in response to determining that the error count corresponding to the given page is in the first predetermined range, use, by the processor, the second calibration scheme to recalibrate the given page in the block.

21. The system of claim 19 , the logic being configured to:

in response to determining that an error correction code failure did not occur when attempting to read the recalibrated given page, determine, by the processor, whether an error count corresponding to the given page is in a second predetermined range; and

in response to determining that the error count corresponding to the given page is in the second predetermined range, send, by the processor, one or more instructions to relocate data stored in the given page.

22. The system of claim 21 , the logic being configured to:

in response to determining that the error count corresponding to the given page is not in the second predetermined range, increment, by the processor, an error-recovery counter which corresponds to the given page;

determine, by the processor, whether the error-recovery counter corresponding to the given page is in a third predetermined range; and

in response to determining that the error-recovery counter corresponding to the given page is in the third predetermined range, send, by the processor, one or more instructions to relocate data stored in the given page.

23. The system of claim 19 , wherein the memory is three-dimensional quad-level-cell NAND Flash, wherein the first number of independent read voltage offset values is less than the second number of independent read voltage offset values.

24. The system of claim 19 , wherein using the first calibration scheme to calibrate the given page in the block includes:

determining one or more read voltages associated with a page type that corresponds to the given page;

determining one or more existing read voltage offset values which correspond to the one or more read voltages;

computing a corrective offset for each of the existing read voltage offset values; and

using the corrective offsets to update the existing read voltage offset values.

25. The system of claim 24 , wherein the corrective offsets are used to update the existing read voltage offset values based on a first mapped relationship which extends between the corrective offsets and the existing read voltage offset values, wherein the first mapped relationship corresponds to the first calibration scheme.