IP Library › Granted Patent US 11,056,481
Granted Patent B2
US 11,056,481 · App. 16/101,953 · Granted Jul 6, 2021

Floating base silicon controlled rectifier

Inventors: Chih-Ting Yeh (Zhudong Township, Hsinchu County, TW); Che-Hao Chuang (Jhudong Township, Hsinchu County, TW)
Assignee: AMAZING MICROELECTRONIC CORP.
H01L27/0262H01L27/0641
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Quick Facts
Patent No.
US 11,056,481
App. No.
16/101,953
Granted
Jul 6, 2021
Kind
B2
Abstract

A floating base silicon controlled rectifier is provided, which at least comprises a first conductivity type layer; a second conductivity type well formed in the first conductivity type layer; a first conductivity type heavily doped region coupled to a first node and formed in the second conductivity type well; and a second conductivity type heavily doped region coupled to a second node and formed in the first conductivity type layer. The first conductivity type and the second conductivity type are opposite. When the first conductivity type is N type, the second conductivity type is P type. Alternatively, when the first conductivity type is P type, the second conductivity type is N type. By employing the proposed present invention, the floating base silicon controlled rectifier acts as a forward diode, and an input capacitance can be greatly reduced.

Claims (9)

1. A whole-chip ESD protection structure, comprising:

a first and second floating base silicon controlled rectifier each comprising:

a first conductivity type substrate;

a second conductivity type well formed in said first conductivity type substrate, said second conductivity type being different than said first conductivity type;

a first conductivity type heavily doped region formed in said second conductivity type well and coupled to a first node, wherein the first node is the only node coupled within the second conductivity type well; and

a second conductivity type heavily doped region formed in said first conductivity type substrate and coupled to a second node, such that said first conductivity type substrate, said second conductivity type well, said first conductivity type heavily doped region and said second conductivity type heavily doped region forms said floating base silicon controlled rectifier;

wherein an anode of said first floating base silicon controlled rectifier is electrically connected to a low voltage level, a cathode of said first floating base silicon controlled rectifier and an anode of said second floating base silicon controlled rectifier are electrically connected to an I/O pin, a cathode of said second floating base silicon controlled rectifier is electrically connected to a high voltage level, and the first and second floating base silicon controlled rectifiers are capable of acting as a forward biased diode, the first and second floating base silicon controlled rectifiers have a small turn-on voltage in a range of 0.7 V-1.0 V and the first and second floating base silicon controlled rectifiers show no snapback effect.

2. The whole-chip ESD protection structure according to claim 1 , wherein said second conductivity type is P type, if said first conductivity type is N type.

3. The whole-chip ESD protection structure according to claim 2 , wherein said first conductivity type substrate is an N type substrate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 14, 2018
From: YEH, CHIH-TING; CHUANG, CHE-HAO
To: AMAZING MICROELECTRONIC CORP.
Reel/Frame 046814/0300 →
Continuity (1)
Related Publication 20200051971A1 · Feb 13, 2020
Cited By (2)
US 12,224,280 US 12,248,019