Semiconductor memory device

1. A semiconductor memory device comprising:

a substrate;

a source structure disposed on a first region of the substrate;

memory cell strings connected to the source structure; and

a capacitor structure disposed on a second region of the substrate,

wherein the source structure is disposed between the first region of the substrate and each of the memory cell strings, and

wherein the capacitor structure is spaced apart from the source structure in a horizontal direction.

2. The semiconductor memory device of claim 1 , wherein a sidewall of the source structure and a sidewall of the capacitor structure face each other.

3. The semiconductor memory device of claim 1 , further comprising:

a lower insulating layer disposed on the substrate; and

transistors disposed in the lower insulating layer, wherein the transistors constitute a peripheral circuit of the semiconductor memory device,

wherein the source structure and the capacitor structure are disposed on the lower insulating layer.

4. A semiconductor memory device comprising:

a substrate;

a source structure disposed on a first region of the substrate;

memory cell strings connected to the source structure; and

a capacitor structure disposed on a second region of the substrate, wherein the capacitor structure is spaced apart from the source structure in a horizontal direction,

wherein the capacitor structure comprises first and second conductive patterns with a sacrificial layer between the first and second conductive patterns.

5. The semiconductor memory device of claim 4 , wherein the sacrificial layer comprises a material having an etching rate different from an etching rate of the first and second conductive patterns.

6. The semiconductor memory device of claim 4 , further comprising:

a first insulating layer between the first conductive pattern and the sacrificial layer;

a second insulating layer between the second conductive pattern and the sacrificial layer;

a first capacitor node contact extending from the substrate through the first conductive pattern, through the first insulating layer, through the sacrificial layer, and through the second insulating layer to electrically connect with the second conductive pattern;

a second capacitor node contact extending from a dummy stack structure through the second conductive pattern and through the second insulating layer to electrically connect with the sacrificial layer; and

a capacitor insulating layer disposed between the first capacitor node contact and the second capacitor node contact, wherein the capacitor insulating layer penetrates the second conductive pattern and the sacrificial layer to separate both the second conductive pattern and the sacrificial layer into a first capacitor electrode electrically connected to the first capacitor node contact and a second capacitor electrode electrically connected to the second capacitor node contact.

7. The semiconductor memory device of claim 4 , wherein the source structure includes:

a first source layer spaced apart from the first conductive pattern in the horizontal direction;

a second source layer spaced apart from the second conductive pattern in the horizontal direction; and

a contact source layer disposed between the first source layer and the second source layer.

8. The semiconductor memory device of claim 7 , wherein the first source layer and the first conductive pattern comprise the same material, and

the second source layer and the second conductive pattern comprise the same material.

9. The semiconductor memory device of claim 4 , further comprising:

a first capacitor node contact extending toward the second conductive pattern from the substrate, wherein the first capacitor node contact penetrates the first conductive pattern and connects to the second conductive pattern;

a second capacitor node contact extending from the second conductive pattern; and

a capacitor insulating layer disposed between the first capacitor node contact and the second capacitor node contact, wherein the capacitor insulating layer penetrates the second conductive pattern and separates the second conductive pattern into a first capacitor electrode and a second capacitor electrode.

10. The semiconductor memory device of claim 9 , wherein the capacitor insulating layer extends toward the first conductive pattern to penetrate the sacrificial layer.

11. The semiconductor memory device of claim 4 , further comprising:

a first capacitor node contact extending toward the substrate from the first conductive pattern; and

a second capacitor node contact extending from the second conductive pattern.

12. The semiconductor memory device of claim 11 , wherein the capacitor structure further includes:

a first insulating layer disposed between the first conductive pattern and the sacrificial layer; and

a second insulating layer disposed between the second conductive pattern and the sacrificial layer,

wherein the sacrificial layer includes silicon.

13. The semiconductor memory device of claim 12 , wherein the second capacitor node contact penetrates the second conductive pattern and the second insulating layer and extends to the inside of the sacrificial layer.

14. The semiconductor memory device of claim 12 , wherein the first capacitor node contact penetrates the first conductive pattern and the first insulating layer and extends to the inside of the sacrificial layer.

15. A semiconductor memory device comprising:

a substrate;

interlayer insulating layers stacked on the substrate, wherein the interlayer insulating layers are spaced apart from each other;

sacrificial insulating layers disposed between the interlayer insulating layers over a second region of the substrate; and

a capacitor structure disposed between the substrate and a dummy stack structure,

wherein the dummy stack structure comprises the interlayer insulating layers and the sacrificial insulating layers, and

wherein the sacrificial insulating layers overlap the capacitor structure.

16. The semiconductor memory device of claim 15 , further comprising:

gate electrodes disposed between the interlayer insulating layers over a first region of the substrate;

a source structure disposed between the substrate and a cell stack structure, wherein the cell stack structure comprises the gate electrodes and the interlayer insulating layers;

a channel layer penetrating the cell stack structure, wherein the channel layer extends to the inside of the source structure; and

a memory layer surrounding an outer wall of the channel layer.

17. The semiconductor memory device of claim 16 , wherein the source structure includes a first source layer, a second source layer on the first source layer, and a contact source layer between the first source layer and the second source layer,

wherein the contact source layer penetrates the memory layer to be in contact with a sidewall of the channel layer.

18. The semiconductor memory device of claim 17 , wherein the capacitor structure comprises:

a first conductive pattern having a sidewall facing the first source layer;

a second conductive pattern having a sidewall facing the second source layer; and

a sacrificial layer between the first conductive pattern and the second conductive pattern.

19. The semiconductor memory device of claim 18 , wherein the sacrificial layer includes a material having an etching rate different from an etching rate of the first source layer and the second source layer.

20. The semiconductor memory device of claim 18 , wherein the capacitor structure further includes:

a first insulating layer disposed between the first conductive pattern and the sacrificial layer; and

a second insulating layer disposed between the second conductive pattern and the sacrificial layer,

wherein the sacrificial layer includes silicon.