Digital to analog converter device and calibration method

1. A digital-to-analog converter (DAC) device comprising:

a current-steering DAC circuitry configured to generate a first signal according to a plurality of least significant bits of an input signal, and generate a second signal according to a plurality of most significant bits of the input signal; and

a calibration circuitry configured to perform a non-binary search algorithm to generate a calibration signal in response to a comparison result of the first signal and the second signal, in order to calibrate the current-steering DAC circuitry according to the calibration signal.

2. The DAC device of claim 1 , wherein the calibration circuitry comprises:

a digital controller circuit configured to perform the non-binary search algorithm according to a detection signal to generate a plurality of first bits, and generate a plurality of second bits of the calibration signal according to the plurality of first bits, wherein the detection signal is configured to indicate the comparison result.

3. The DAC device of claim 2 , wherein the digital controller circuit comprises:

a calibration circuit configured to perform the non-binary search algorithm according to the detection signal to generate the plurality of first bits; and

a codec circuit configured to convert the plurality of first bits to be the plurality of second bits.

4. The DAC device of claim 2 , wherein the calibration circuitry further comprises:

a detector circuit configured to compare the first signal and the second signal, to generate the detection signal; and

a digital-to-analog converter circuit configured to generate a compensation signal according to the plurality of second bits of the calibration signal, to calibrate the current-steering DAC circuitry.

5. The DAC device of claim 4 , wherein the DAC circuit is further configured to generate an adjustment signal according to the plurality of first bits to adjust the second signal, and the detector circuit is further configured to compare the first signal and the adjusted second signal, to update the detection signal.

6. The DAC device of claim 4 , wherein the non-binary search algorithm sets a redundancy range to at least one bit of the plurality of first bits, to tolerate a mistake of the detector circuit.

7. The DAC device of claim 1 , wherein the current-steering DAC circuitry comprises:

a first DAC circuit configured generate the first signal according to the plurality of least significant bits; and

a second DAC circuit configured generate the second signal according to the plurality of most significant bits.

8. The DAC device of claim 7 , wherein each of the first DAC circuit and the second DAC circuit is implemented by a current-steering DAC circuit.

9. A calibration method suitable for a current-steering DAC circuitry, wherein the calibration method comprises:

generating a first signal according to a plurality of least significant bits of an input signal by the current-steering DAC circuitry, and generating a second signal according to a plurality of most significant bits of the input signal by the current-steering DAC circuitry; and

in response to the first signal and the second signal, performing a non-binary search algorithm to generate a calibration signal, and calibrating the current-steering DAC circuitry according to the calibration signal.

10. The calibration method of claim 9 , wherein in response to a comparison result of the first signal and the second signal, performing the non-binary search algorithm to generate the calibration signal comprises:

performing the non-binary search algorithm according to a detection signal to generate a plurality of first bits, wherein the detection signal is configured to indicate the comparison result; and

generating a plurality of second bits of the calibration signal according to the plurality of the first bits.

11. The calibration method of claim 10 , wherein generating the plurality of second bits of the calibration signal according to the plurality of first bits comprises:

performing an encoding/decoding operation to the plurality of first bits, to generate the plurality of second bits.

12. The calibration method of claim 10 further comprising:

comparing the first signal and the second signal by a detector circuit, to generate the detection signal; and

generating a compensation signal according to the plurality of second bits of the calibration signal by a DAC circuit, to calibrate the current-steering DAC circuitry.

13. The calibration method of claim 12 , wherein the DAC circuit is further configured to generate an adjustment signal according to the plurality of first bits to adjust the second signal, and the detector circuit is configured to compare the first signal and the adjusted second signal, to update the detection signal.

14. The calibration method of claim 12 , wherein the non-binary search algorithm sets a redundancy range to at least one bit of the plurality of first bits, to tolerate a mistake of the detector circuit.

15. The calibration method of claim 9 , wherein generating the first signal according to the plurality of least significant bits of the input signal by the current-steering DAC circuitry, and generating the second signal according to the plurality of most significant bits of the input signal by the current-steering DAC circuitry comprises:

generating the first signal according to the plurality of least significant bits by a first DAC circuit; and

generating the second signal according to the plurality of most significant bits by a second DAC circuit.

16. The calibration method of claim 15 , wherein the each of the first DAC circuit and the second DAC circuit is implemented by a current-steering DAC circuit.