Time-interleaved analog-to-digital converter with calibration
An apparatus is provided to calibrate an analog-to-digital converter (ADC). The apparatus includes a calibration circuitry coupled to an output of the ADC, wherein the calibration circuitry is to identify a maximum value and minimum value of the output of the ADC, and is to calibrate one or more performance parameters of the ADC according to the maximum and minimum values. The performance parameters include: gain of the ADC, offset of the ADC, and timing skew between the ADC and a neighboring ADC.
1. An apparatus comprising:
an analog-to-digital converter (ADC) having a first input to receive an analog signal and an output to provide a digital representation of the analog signal; and
a calibration circuitry having an input coupled to an output of the ADC, wherein the calibration circuitry includes a multiplexer coupled to the output of the ADC, wherein the multiplexer is to select between a first calibration mode and second calibration mode wherein an output of the calibration circuitry is coupled to a second input of the ADC, and wherein the output of the calibration circuitry is to adjust a delay of a sampling clock to the ADC.
2. The apparatus of claim 1 , wherein the calibration circuitry includes a first circuitry coupled to an output of the multiplexer, and wherein the first circuitry is to determine a maximum value of the output of the multiplexer.
3. The apparatus of claim 2 , wherein the calibration circuitry includes a second circuitry coupled to an output of the multiplexer, and wherein the second circuitry is to determine a minimum value of the output of the multiplexer.
4. The apparatus of claim 3 , wherein the calibration circuitry comprises a third circuitry to determine an average of the maximum and minimum values.
5. The apparatus of claim 4 , wherein the calibration circuitry comprises a fourth circuitry to determine a difference between the maximum and minimum values.
6. The apparatus of claim 5 , wherein the calibration circuitry comprises a fifth circuitry to apply the difference to calibrate gain of the ADC.
7. The apparatus of claim 6 , wherein the fifth circuitry is to output a modified digital representation of the analog signal.
8. The apparatus of claim 7 , wherein the modified digital representation is a first modified digital representation, and wherein the calibration circuitry comprises a sixth circuitry to receive the first modified digital representation of the analog signal, and to apply the average to calibrate an offset of the ADC and to generate a second modified digital representation of the analog signal with calibrated offset.
9. The apparatus of claim 8 , wherein the ADC is a first ADC, wherein the apparatus comprises a seventh circuitry to subtract the second modified digital representation from a third modified digital representation to generate a subtracted output, wherein the third modified digital representation has calibrated gain and offset associated with a second ADC, and wherein the subtracted output is received as input to the multiplexer.
10. The apparatus of claim 9 , wherein the multiplexer is to select the output of the ADC and to provide it as the output of the multiplexer in the first calibration mode, and wherein the multiplexer is to select the subtracted output as the output of the multiplexer in the second calibration mode.
11. The apparatus of claim 5 , wherein the calibration circuitry comprises an eighth circuitry to receive the difference and to compare the difference with a threshold, and to adjust a delay of a sampling clock to the ADC, via the second input, according to a result of the comparison.
12. An apparatus comprising:
a first an analog-to-digital converter (ADC) having an input to receive a first analog signal and an output to provide a first digital representation of the first analog signal;
a second ADC having an input to receive a second analog signal and an output to provide a second digital representation of the second analog signal;
a first calibration circuitry; and
a second calibration circuitry, wherein the first calibration circuitry is to receive the first digital representation and an output of the second calibration circuitry, wherein the first calibration circuitry is to generate a first sampling control for the first ADC, wherein the second calibration circuitry is to receive the second digital representation and an output of a third calibration circuitry, and wherein the second calibration circuitry is to generate a second sampling control for the second ADC.
13. The apparatus of claim 12 , wherein the first sampling control is to calibrate one or more performance parameters of the first ADC, and wherein the second sampling control is to calibrate one or more performance parameters of the second ADC.
14. The apparatus of claim 13 , wherein the one or more performance parameters include: gain of the first or second ADC, offset of the first or second ADC, and timing skew between the first ADC and the second ADC.
15. The apparatus of claim 12 , wherein the first or second calibration circuitries includes a first circuitry coupled to an output of a multiplexer, and wherein the first circuitry is to determine a maximum value of the output of the multiplexer.
16. The apparatus of claim 15 , wherein the first or second calibration circuitries include a second circuitry coupled to an output of the multiplexer, and wherein the second circuitry is to determine a minimum value of the output of the multiplexer.
17. The apparatus of claim 12 , wherein the first and second calibration circuitries are to operate in parallel to the operation of the first and second ADCs.
18. A system comprising:
a memory;
a processor coupled to the memory; and
a wireless interface communicatively coupled to the processor, wherein the processor includes:
an analog-to-digital converter (ADC) having a first input to receive an analog signal and an output to provide a digital representation of the analog signal; and
a calibration circuitry having an input coupled to an output of the ADC, wherein the calibration circuitry includes a multiplexer coupled to the output of the ADC, wherein the multiplexer is to select between a first calibration mode and second calibration mode, wherein an output of the calibration circuitry is coupled to a second input of the ADC, and wherein the output of the calibration circuitry is to adjust a delay of a sampling clock to the ADC.
19. The system of claim 18 , wherein the calibration circuitry includes a first circuitry coupled to an output of the multiplexer, and wherein the first circuitry is to determine a maximum value of the output of the multiplexer.
20. The system of claim 19 , wherein the calibration circuitry includes a second circuitry coupled to an output of the multiplexer, and wherein the second circuitry is to determine a minimum value of the output of the multiplexer.