Method, apparatus, and system for reducing pipeline stalls due to address translation misses

1. An apparatus, comprising:

a memory access instruction pipeline;

a translation lookaside buffer (TLB) coupled to the memory access instruction pipeline; and

a TLB miss queue coupled to the TLB and to the memory access instruction pipeline;

wherein the TLB miss queue is configured to selectively store both:

a first memory access instruction that has been removed from the memory access instruction pipeline as a result of the first memory access instruction missing in the TLB; and

information associated with the first memory access instruction.

2. The apparatus of claim 1 , wherein the TLB miss queue is further configured to reintroduce the first memory access instruction to the memory access instruction pipeline associated with a return of an address translation related to the first memory access instruction.

3. The apparatus of claim 1 , wherein the TLB miss queue is further configured to compare a memory page associated with the first memory access instruction to the memory pages associated with all the active entries of the TLB miss queue; and

to generate a translation request if the memory page associated with the first memory access instruction does not match the memory pages associated with any of the active entries of the TLB miss queue, or

to suppress a translation request if the memory page associated with the first memory access instruction matches any of the memory pages associated with any of the active entries of the TLB miss queue.

4. The apparatus of claim 1 , wherein the TLB miss queue is further configured to compare a memory page associated with the first memory access instruction to address translations that are expected to be received, and if the address translation corresponding to the memory page associated with the first memory access instruction is expected to be received within a particular number of cycles, suppress storing the first memory access instruction and associated information in the TLB miss queue and stall the memory access instruction pipeline until the address translation is received.

5. The apparatus of claim 1 , wherein the memory access instructions comprise load instructions and store instructions.

6. The apparatus of claim 5 , wherein the TLB miss queue is a unified TLB miss queue configured to store both load instructions and store instructions.

7. The apparatus of claim 5 , wherein the TLB miss queue comprises a separate load TLB miss queue configured to store load instructions that miss in the TLB and associated information and a store TLB miss queue configured to store instructions that miss in the TLB and associated information.

8. The apparatus of claim 7 , wherein the load TLB miss queue and the store TLB miss queue are heterogeneous designs.

9. The apparatus of claim 2 , wherein the information associated with the first memory access instruction does not comprise hazard detection information, and wherein the TLB miss queue is further configured to reintroduce the first memory access instruction to the memory access instruction pipeline such that the memory access instruction pipeline will perform hazard detection on the first memory access instruction as if it were a new instruction.

10. The apparatus of claim 2 , wherein the information associated with the first memory access instruction comprises hazard detection information, and wherein the TLB miss queue is further configured to reintroduce the first memory access instruction to the memory access instruction pipeline such that the memory access instruction pipeline does not perform hazard detection on the first memory access instruction as if it were a new instruction.

11. The apparatus of claim 2 , wherein the TLB miss queue is further configured to reintroduce the first memory access instruction to the memory access instruction pipeline a number of cycles in advance of the return of the address translation related to the first memory access instruction.

12. The apparatus of claim 1 , wherein the TLB miss queue is further configured to reintroduce the first memory access instruction to a second memory access instruction pipeline associated with a return of an address translation related to the first memory access instruction.

13. The apparatus of claim 1 , integrated into a computing device.

14. The apparatus of claim 13 , the computing device further integrated into a device selected from the group consisting of a mobile phone, a communications device, a computer, a server, a laptop, a tablet, a personal digital assistant, a music player, a video player, an entertainment unit, and a set top box.

15. A method comprising:

removing, from a memory access instruction pipeline, a first memory access instruction that has missed in a translation lookaside buffer (TLB) to make the memory access instruction pipeline available to other memory access instructions; and

selectively storing both the first memory access instruction and associated information in a TLB miss queue, which is coupled to the TLB and to the memory access instruction pipeline, while awaiting an address translation for the first memory access instruction.

16. The method of claim 15 , further comprising reintroducing the first memory access instruction to the memory access instruction pipeline associated with a return of the address translation associated with the first memory access instruction.

17. The method of claim 15 , further comprising:

comparing a memory page associated with the first memory address instruction to the memory pages associated with all the active entries of the TLB miss queue; and

generating a translation request for the first memory access instruction if the memory page associated with the first memory access instruction does not match the memory pages associated with any of the active entries of the TLB miss queue; or

suppressing generating a translation request for the first memory access instruction if the memory page associated with the first memory access instruction matches any of the memory pages associated with any of the active entries of the TLB miss queue.

18. The method of claim 15 , further comprising:

comparing a memory page associated with the first memory access instruction to address translations that are expected to be received; and

if the address translation corresponding to the memory page associated with the first memory access instruction is expected to be received within a particular number of cycles, suppressing storing the first memory access instruction and associated information in the TLB miss queue and stalling the memory access instruction pipeline until the address translation corresponding to the memory page associated with the first memory access instruction is received.

19. The method of claim 16 , wherein the information associated with the first memory access instruction does not comprise hazard detection information, and wherein reintroducing the first memory access instruction to the memory access instruction pipeline is performed at a stage of the memory access instruction pipeline such that the memory access instruction pipeline will perform hazard detection on the first memory access instruction after its reintroduction as if it were a new instruction.

20. The method of claim 16 , wherein the information association with the first memory access instruction comprises hazard detection information, and wherein reintroducing the first memory access instruction to the memory access instruction pipeline is performed at a stage of the memory access instruction pipeline such that the memory access instruction pipeline will not perform hazard detection on the first memory access instruction after its reintroduction as if it were a new instruction.

21. The method of claim 16 , wherein reintroducing the first memory access instruction to the memory access instruction pipeline is performed a number of cycles in advance of the return of the address translation associated with the first memory access instruction.

22. The method of claim 15 , further comprising reintroducing the first memory access instruction to a second memory access instruction pipeline associated with a return of the address translation associated with the first memory access instruction.

23. A non-transitory computer readable medium comprising instructions which, when executed by a processor, cause the processor to:

remove, from a memory access instruction pipeline, a first memory access instruction that has missed in a translation lookaside buffer (TLB) to make the memory access instruction pipeline available to other memory access instructions; and

selectively store both the first memory access instruction and associated information in a TLB miss queue, which is coupled to the TLB and to the memory access instruction pipeline, while awaiting an address translation for the first memory access instruction.

24. An apparatus comprising:

means for executing memory access instructions;

means for caching address translations coupled to the means for executing memory access instructions; and

means for storing instructions that miss in the means for caching address translations coupled to the means for caching address translations and to the means for executing memory access instructions;

wherein the means for storing instructions that miss is configured to selectively store both:

a first memory access instruction that has been removed from the means for executing memory access instructions as a result of the first memory access instruction missing in the means for caching address translations; and

information associated with the first memory access instruction.