Memory system capable of improving stability of a data read operation of interface circuit, and method of operating the memory system
The present technology includes a memory system and a method of operating the memory system. The memory system includes a memory device including an interface circuit, the interface circuit storing first system data, and a semiconductor memory; and a controller configured to output a read enable signal and a first read command for the first system data to the memory device. The semiconductor memory transfers a data strobe signal to the interface circuit in response to the read enable signal, the interface circuit reads the first system data in response to the first read command and transmits the read first system data to the controller in synchronization with the data strobe signal.
1. A memory system comprising:
a memory device including an interface circuit, the interface circuit storing first system data, and a semiconductor memory, the semiconductor memory storing second system data; and
a controller configured to output a read enable signal and a first read command for the first system data to the memory device,
wherein the semiconductor memory transfers a data strobe signal to the interface circuit in response to the read enable signal, and
wherein the interface circuit reads the first system data in response to the first read command and transmits the read first system data to the controller in synchronization with the data strobe signal.
2. The memory system according to claim 1 , wherein the interface circuit transfers the read enable signal to the semiconductor memory, and
wherein the semiconductor memory includes a data strobe signal generation circuit for generating the data strobe signal.
3. The memory system according to claim 1 , wherein the interface circuit transmits the first read command to the semiconductor memory together with the read enable signal.
4. The memory system according to claim 3 , wherein the semiconductor memory reads and provides the second system data to the interface circuit together with the data strobe signal in response to the first read command.
5. The memory system according to claim 4 , wherein the interface circuit blocks the second system data.
6. The memory system according to claim 4 , wherein the interface circuit comprises:
a timing control circuit configured to control a timing of the first read command and the read enable signal received from the controller and output the first read command and the read enable signal;
a processor configured to receive and parse the first read command output from the controller and generate a blocking control signal and a data read signal when the first read command corresponds to the interface circuit as a result of the parsing;
a data storage circuit configured to store the first system data, and output the first system data in synchronization with the data strobe signal in response to the data read signal; and
a blocking control circuit configured to transmit to the semiconductor memory the first read command and the read enable signal received from the timing control circuit, receive the data strobe signal and the second system data from the semiconductor memory, and block the second system data in response to the blocking control signal.
7. The memory system according to claim 4 ,
wherein the first system data is status data, read training data, or option parameter data of the interface circuit, and
wherein the second system data is the status data, the read training data, or the option parameter data of the semiconductor memory.
8. The memory system according to claim 4 ,
wherein the controller is further configured to output a second read command for second system data stored in the semiconductor memory,
wherein the interface circuit transfers the second read command and the read enable signal to the semiconductor memory, and
wherein the interface circuit transfers the second system data and the data strobe signal from the semiconductor memory to the controller.