Memory device
A memory device includes a substrate including first and second regions, the first region having first wordlines and first bitlines, and the second region having second wordlines and second bitlines, a first memory cell array including first memory cells in the first region, the first memory cell array having volatility, and each of the first memory cells including a cell switch having a first channel region adjacent to a corresponding first wordline of the first wordlines, and a capacitor connected to the cell switch, and a second memory cell array including second memory cells in the second region, the second memory cell array having non-volatility, and each of the second memory cells including a second channel region adjacent to a corresponding second wordline of the second wordlines, and a ferroelectric layer between the corresponding second wordline of the second wordlines and the second channel region.
1. A memory device, comprising:
a substrate including a first region and a second region, the first region having first wordlines and first bitlines, and the second region having second wordlines and second bitlines;
a first memory cell array including first memory cells in the first region, the first memory cell array having volatility, and each of the first memory cells including:
a cell switch having a first channel region adjacent to a corresponding first wordline of the first wordlines, and
a capacitor connected to the cell switch; and
a second memory cell array including second memory cells in the second region, the second memory cell array having non-volatility, and each of the second memory cells including:
a second channel region adjacent to a corresponding second wordline of the second wordlines, and
a ferroelectric layer between the corresponding second wordline of the second wordlines and the second channel region.
2. The memory device as claimed in claim 1 , wherein the first wordlines and the second wordlines are embedded in the substrate.
3. The memory device as claimed in claim 1 , wherein the first wordlines are embedded within the substrate, and the second wordlines are on the substrate.
4. The memory device as claimed in claim 1 , further comprising a controller configured to control the first memory cell array and the second memory cell array, the controller to activate the first memory cell array and to deactivate the second memory cell array in a first mode, and to store data of the first memory cell array in the second memory cell array in a second mode different from the first mode.
5. The memory device as claimed in claim 4 , wherein the controller is to operate in the second mode in every predetermined period.
6. The memory device as claimed in claim 4 , further comprising transfer switches between the first region and the second region, the transfer switches connecting the first wordlines and the second wordlines to each other or disconnecting the first wordlines and the second wordlines from each other.
7. The memory device as claimed in claim 6 , wherein the controller is to turn off the transfer switches in the first mode, and to turn on the transfer switches and to read data of the first memory cells and to store the read data in the second memory cells in the second mode.
8. The memory device as claimed in claim 1 , wherein the first memory cells are dynamic random access memory cells, and the second memory cells are ferroelectric random access memory cells.
9. The memory device as claimed in claim 1 , wherein the second memory cells are at a same height as the cell switch of the first memory cells.
10. The memory device as claimed in claim 1 , wherein the second memory cells are the first memory cells.
11. The memory device as claimed in claim 10 , wherein the first channel region and the second channel region include different materials.
12. The memory device as claimed in claim 11 , wherein the second channel region includes indium-gallium-zinc oxide (IGZO).
13. The memory device as claimed in claim 10 , wherein the corresponding second wordline of the second wordlines is below the second channel region in each of the second memory cells.