Semiconductor structure and manufacturing method for the same
View Patent ↗The present disclosure provides a semiconductor structure, including a bottom terminal, a middle terminal over the bottom terminal and separated from the bottom terminal by a high-k dielectric layer, a top terminal over the middle terminal and separated from the middle terminal by the high-k dielectric layer, and a silicon nitride layer over the top terminal and directly on the high-k dielectric layer.
1. A semiconductor structure, comprising:
a bottom terminal;
a middle terminal over the bottom terminal and separated from the bottom terminal by a high-k dielectric layer;
a top terminal over the middle terminal and separated from the middle terminal by the high-k dielectric layer;
a silicon nitride layer over the top terminal and directly on the high-k dielectric layer;
a passivation layer over the silicon nitride layer;
a conductive via penetrating bottom terminal;
a spacer on a sidewall of the conductive via, wherein the spacer comprises titanium nitride;
a conductive post over the passivation layer; and
a barrier layer at a sidewall of the conductive via and extending over a portion of the passivation layer, the barrier layer being free from separating the conductive via and the conductive post,
wherein a thickness of the passivation layer is greater than a thickness of the silicon nitride layer.
2. The semiconductor structure of claim 1 , wherein the conductive via penetrates the bottom terminal.
3. The semiconductor structure of claim 2 , wherein the conductive via is composed of aluminum-copper.
4. The semiconductor structure of claim 1 , wherein the spacer contacts the high-k dielectric layer and at least one of the bottom terminal, the middle terminal, and the top terminal.
5. The semiconductor structure of claim 1 , wherein the spacer contacts with the silicon nitride layer.
6. The semiconductor structure of claim 1 , wherein a thickness of the silicon nitride layer is comparable to a thickness of one of the bottom terminal, the middle terminal, and the top terminal.
7. The semiconductor structure of claim 1 , wherein the high-k dielectric layer comprises a tri-layer of zirconium oxide-aluminum oxide-zirconium oxide.
8. A semiconductor structure, comprising:
a bottom terminal;
a middle terminal over the bottom terminal and separated from the bottom terminal by a high-k dielectric layer;
a top terminal over the middle terminal and separated from the middle terminal by the high-k dielectric layer;
a silicon nitride layer over the top terminal;
a passivation layer over the silicon nitride layer;
a conductive via penetrating the bottom terminal, the silicon nitride layer, and the passivation layer, and in connection with a conductive post over the passivation layer;
a spacer on a sidewall of the conductive via, wherein the spacer comprises titanium nitride; and
a barrier layer in contact with the spacer and extends over a portion of the passivation layer, the barrier layer being composed of material different from that of the spacer.
9. The semiconductor structure of claim 8 , wherein the conductive via is composed of aluminum-copper.
10. The semiconductor structure of claim 8 , wherein the silicon nitride layer over the top terminal is directly on the high-k dielectric layer.
11. A method for fabricating a semiconductor structure, comprising:
forming a bottom terminal over a top metal layer;
forming a middle terminal over the bottom terminal;
forming a top terminal over the middle terminal;
forming a high-k dielectric layer between the bottom terminal and the middle terminal, and between the middle terminal and the top terminal;
forming a silicon nitride layer over the top terminal;
forming a passivation layer over the silicon nitride layer;
forming a via trench penetrating the bottom terminal, the silicon nitride layer, the high-k dielectric layer, and the passivation layer;
forming a spacer over a sidewall of the via trench and over the top terminal; and
etching the spacer to remove a portion of the spacer over the top terminal.
12. The method of claim 11 , wherein forming the via trench penetrating the bottom terminal, the silicon nitride layer, the high-k dielectric layer, and the passivation layer comprises performing dry etch to remove the silicon nitride layer, the high-k dielectric layer, and at least the bottom terminal.
13. The method of claim 11 , further comprising applying a cleaning solution in the via trench prior to forming the spacer.
14. The method of claim 11 , further comprising filling conductive material in the trench after forming the spacer.
15. The method of claim 11 , wherein etching the spacer further comprises removing a portion of the spacer at a bottom of the via trench.
16. The method of claim 11 , further comprising forming a barrier layer over a sidewall of the via trench and over the passivation layer after forming the spacer.
17. The method of claim 16 , further comprising patterning a photomask over the passivation layer prior to forming the barrier layer.
18. The method of claim 11 , wherein forming the silicon nitride layer over the top terminal comprises forming a conformal layer over the high-k dielectric layer and the top terminal.
19. The method of claim 18 , wherein a thickness of the silicon nitride layer is comparable to a thickness of the bottom terminal, the middle terminal, or the top terminal.
20. The method of claim 18 , wherein a thickness of the silicon nitride layer is in a range of from about 500 Angstrom to about 1,000 Angstrom.