Semiconductor device
A RESURF isolation structure surrounds an outer periphery of the high-side circuit region to isolate the high-side circuit region and the low-side circuit region from each other. The RESURF isolation structure includes a high-voltage isolation region, a high-voltage N-ch MOS, and a high-voltage P-ch MOS. The high-voltage isolation region, the high-voltage N-ch MOS, and the high-voltage P-ch MOS include a plurality of field plates ( 9,19 a, 19 b, 19 c ). An inner end of the field plate ( 19 c ) of the high-voltage P-ch MOS located closest to the low-side circuit region is positioned closer to the low-side circuit region than an inner end of the field plate ( 19 b ) of the high-voltage N-ch MOS located closest to the low-side circuit region.
1. A semiconductor device comprising:
a high-side circuit region;
a low-side circuit region; and
a reduced surface field (RESURF) isolation structure surrounding an outer periphery of the high-side circuit region to isolate the high-side circuit region and the low-side circuit region from each other, wherein
the RESURF isolation structure includes a high-voltage isolation region, a high-voltage n-channel metal-oxide semiconductor (N-ch MOS), and a high-voltage p-channel metal-oxide semiconductor (P-ch MOS),
the high-voltage isolation region, the high-voltage N-ch MOS, and the high-voltage P-ch MOS include a thermal oxide film, and a plurality of field plates provided on the thermal oxide film,
the plurality of field plates includes at least a first field plate directly covering an inner end portion of the thermal oxide film in each of the high-voltage isolation region, the high-voltage N-ch MOS, and the high-voltage P-ch MOS; and a second field plate directly covering an outer end portion of the thermal oxide film in each of the high-voltage isolation region, the high-voltage N-ch MOS, and the high-voltage P-ch MOS, and
an inner end of the second field plate of the high-voltage P-ch MOS located closest to the low-side circuit region is positioned closer to the low-side circuit region than an inner end of the second field plate of the high-voltage N-ch MOS located closest to the low-side circuit region.
2. The semiconductor device according to claim 1 , wherein
the plurality of field plates contain a spiral poly silicon portion provided on the thermal oxide film, and
parts of the spiral polysilicon portion in the high-voltage P-ch MOS are spaced apart at larger intervals than those of parts of the spiral polysilicon portion in the high-voltage N-ch MOS.
3. The semiconductor device according to claim 1 , wherein
the plurality of field plates contain a spiral polysilicon portion provided on the thermal oxide film,
intervals of parts of the spiral polysilicon portion are same in the high-voltage N-ch MOS and the high-voltage P-ch MOS, and
the spiral polysilicon portion in the high-voltage P-ch MOS is positioned closer to the low-side circuit region than the spiral polysilicon portion in the high-voltage N-ch MOS.
4. The semiconductor device according to claim 1 , wherein
the plurality of field plates contain a polysilicon portion and a metal wiring layer provided on the thermal oxide film and capacitively-coupled to each other.
5. A semiconductor device comprising:
a high-side circuit region;
a low-side circuit region; and
a reduced surface field (RESURF) isolation structure surrounding an outer periphery of the high-side circuit region to isolate the high-side circuit region and the low-side circuit region from each other, wherein
the RESURF isolation structure includes a high-voltage isolation region, a high-voltage n-channel metal-oxide semiconductor (N-ch MOS), and a high-voltage p-channel metal-oxide semiconductor (P-ch MOS),
the high-voltage isolation region, the high-voltage N-ch MOS, and the high-voltage P-ch MOS include a thermal oxide film, and a plurality of field plates containing a spiral polysilicon portion provided on the thermal oxide film,
a field plate located closest to the low-side circuit region in the high-voltage P-ch MOS is shorter than a field plate located closest to the low-side circuit region in the high-voltage N-ch MOS, and
a distance between the field plate closest to the low-side circuit region and the field plate closest to the high-side circuit region is same in all of the high-voltage isolation region, the high-voltage N-ch MOS, and the high-voltage P-ch MOS.
6. A semiconductor device comprising:
a high-side circuit region;
a low-side circuit region; and
a reduced surface field (RESURF) isolation structure surrounding an outer periphery of the high-side circuit region to isolate the high-side circuit region and the low-side circuit region from each other, wherein
the RESURF isolation structure includes a high-voltage isolation region, a high-voltage n-channel metal-oxide semiconductor (N-ch MOS), and a high-voltage p-channel metal-oxide semiconductor (P-ch MOS),
the high-voltage isolation region, the high-voltage N-ch MOS, and the high-voltage P-ch MOS include a thermal oxide film, and a plurality of field plates provided on the thermal oxide film, and
a field plate located closest to the low-side circuit region in the high-voltage P-ch MOS is shorter than a field plate located closest to the low-side circuit region in the high-voltage N-ch MOS.