Semiconductor device

1. A semiconductor device, comprising:

a first inter-layer dielectric (ILD) layer;

a first metallization pattern in the first ILD layer;

an etch stop layer over the first ILD layer;

a metal-containing compound layer over the etch stop layer, wherein the etch stop layer has a portion extending beyond an edge of the metal-containing compound layer;

a memory cell over the metal-containing compound layer and comprising a bottom electrode, a resistance switching element over the bottom electrode, and a top electrode over the resistance switching element;

a second metallization pattern extending through the portion of the etch stop layer to the first metallization pattern; and

a second ILD layer laterally surrounding the second metallization pattern, wherein a top surface of the portion of the etch stop layer is in contact with the second ILD layer.

2. The semiconductor device of claim 1 , wherein the edge of the metal-containing compound layer is in contact with a side surface of the second ILD layer.

3. The semiconductor device of claim 1 , wherein the second metallization pattern is separated from the metal-containing compound layer.

4. The semiconductor device of claim 1 , further comprising:

a bottom electrode via below the memory cell and in the etch stop layer and the metal-containing compound layer, wherein the bottom electrode via is in contact with the metal-containing compound layer.

5. The semiconductor device of claim 1 , wherein a top surface of the second metallization pattern is higher than a top surface of the resistance switching element of the memory cell.

6. The semiconductor device of claim 1 , wherein the metal-containing compound layer is an aluminum-based layer.

7. A semiconductor device, comprising:

an inter-layer dielectric (ILD) layer;

a conductive feature in the ILD layer;

a memory cell over the conductive feature, wherein the memory cell comprises a bottom electrode, a resistance switching element over the bottom electrode, and a top electrode over the resistance switching element;

a metal-containing compound layer between the memory cell and the conductive feature, and spaced apart from the ILD layer; and

a dielectric layer between the memory cell and the metal-containing compound layer, wherein a top surface of the metal-containing compound layer is in contact with the dielectric layer.

8. The semiconductor device of claim 7 , further comprising:

a dielectric etch stop layer between the metal-containing compound layer and the conductive feature, wherein the dielectric etch stop layer spaces the metal-containing compound layer from the ILD layer.

9. The semiconductor device of claim 8 , wherein a top surface of the conductive feature and a top surface of the ILD layer are in contact with a bottom surface of the dielectric etch stop layer.

10. The semiconductor device of claim 7 , wherein the dielectric layer has a stepped top surface with an upper step in contact with a bottom surface of the bottom electrode of the memory cell and a lower step lower than the bottom surface of the bottom electrode of the memory cell.

11. The semiconductor device of claim 7 , wherein the metal-containing compound layer is a metal oxide layer.

12. The semiconductor device of claim 7 , wherein the metal-containing compound layer is an aluminum-based layer.

13. A semiconductor device, comprising:

an inter-layer dielectric (ILD) layer;

a first conductive feature and a second conductive feature in the ILD layer;

a first bottom electrode via and a second bottom electrode via respectively over the first and second conductive features;

a first memory cell and a second memory cell respectively over the first and second bottom electrode vias, wherein each of the first and second memory cells comprises a bottom electrode, a resistance switching element over the bottom electrode, and a top electrode over the resistance switching element;

a metal-containing compound layer in contact with a sidewall of the first bottom electrode via and a sidewall of the second bottom electrode via, and separated from the first and second conductive features; and

an etch stop layer below the metal-containing compound layer, wherein the etch stop layer is in contact with the sidewall of the first bottom electrode via, the sidewall of the second bottom electrode via, and the first and second conductive features.

14. The semiconductor device of claim 13 , further comprising:

a dielectric layer over the metal-containing compound layer, wherein the dielectric layer is in contact with the sidewall of the first bottom electrode via and the sidewall of the second bottom electrode via.

15. The semiconductor device of claim 14 , wherein the dielectric layer is further in contact with the bottom electrode of the first and second memory cells.

16. The semiconductor device of claim 13 , further comprising:

a spacer laterally surrounding the first memory cell and the second memory cell.

17. The semiconductor device of claim 16 , further comprising:

a dielectric layer between the spacer and the metal-containing compound layer, wherein the dielectric layer separates the spacer apart from the metal-containing compound layer.

18. The semiconductor device of claim 1 , wherein the metal-containing compound layer extends beyond a sidewall of the bottom electrode.

19. The semiconductor device of claim 7 , wherein the metal-containing compound layer is spaced apart from the conductive feature.

20. The semiconductor device of claim 13 , comprising:

a third conductive feature in the ILD layer, wherein the first and second conductive features are at least partially covered by the metal-containing compound layer, and the third conductive feature is free of coverage of the metal-containing compound layer.