System and method for power management of a computing system with a plurality of islands

1. A computing system comprising:

an island ( 102 ) comprising a group of circuits capable of operating in one of a plurality of operating modes, wherein in a first of the operating modes the circuits of the island are adapted to receive a first voltage and/or a first clock signal of a first frequency, and in a second of the operating modes the circuits of the island are adapted to receive a second voltage different from the first voltage and/or a second clock signal of a second frequency different from the first frequency, the island being coupled to an island control circuit ( 122 ), the island control circuit receiving the first and/or second clock signals from a first clock generation circuit and supplying the first and/or second clock signals to the island; and

a second clock generation circuit ( 902 ) supplying a further clock signal (PCLK) to the island control circuit ( 122 ) for controlling a change of mode of the island, the second clock generation circuit ( 902 ) being configured to:

select one of a plurality of clock frequencies for the further clock signal (PCLK), the selection being based on the change of operating mode to be applied; and

select a first clock frequency for the further clock signal (PCLK) when the change of mode is of a first type, and to select a second clock frequency faster than the first clock frequency for the further clock signal (PCLK) when the change of mode is of a second type, the first type of change of mode being longer to implement that the second type of change of mode.

2. The computing system of claim 1 , wherein the first type of change of mode involves a change to the voltage supplied to the island by a voltage supply circuit ( 108 , 110 ), and the second type of change of mode does not involve a change to the voltage supplied to the island.

3. The computing system of claim 1 , wherein the second clock generation circuit ( 902 ) comprises a ring oscillator ( 1004 ).

4. The computing system of claim 1 , wherein the second clock generation circuit ( 902 ) comprises:

a frequency divider ( 1006 ) configured to divide the frequency of an oscillating signal (CK_RO) to generate a plurality of clock signals (CK_ 1 to CK_N) each at a different one of said plurality of clock frequencies; and

a multiplexer ( 1008 ) configured to select one of said plurality of clock signals to form said further clock signal (PCLK).

5. The computing system of claim 4 , wherein the second clock generation circuit ( 902 ) further comprises a controller ( 1002 ) configured to generate a selection signal (F_SEL) for controlling the multiplexer ( 1008 ) to select the further clock signal (PCLK).

6. The computing system of claim 5 , wherein the controller ( 1002 ) is further configured to generate an enable signal (EN) for selectively activating the generation of said oscillating signal (CK_RO).

7. The computing system of claim 1 , further comprising at least one further island ( 104 , 106 ) each having a corresponding island control circuit ( 124 , 126 ), wherein the second clock generation circuit ( 902 ) is common for all of the island control circuits ( 122 , 124 , 126 ).

8. The computing system of claim 7 , wherein the second clock generation circuit ( 902 ) is coupled to all of the island control circuits ( 122 , 124 , 126 ) via a bus ( 116 ) via which the further clock signal (PCLK) is transmitted.

9. A method of modifying an operating mode of an island ( 102 ) of a computing system, the island comprising a group of circuits capable of operating in one of a plurality of operating modes, wherein in a first of the operating modes the circuits of the island are adapted to receive a first voltage and/or a first clock signal of a first frequency, and in a second of the operating modes the circuits of the island are adapted to receive a second voltage different from the first voltage and/or a second clock signal of a second frequency different from the first frequency, the island being coupled to an island control circuit ( 122 ), the island control circuit receiving the first and/or second clock signals from a first clock generation circuit and supplying the first and/or second clock signals to the island, the method comprising:

selecting one of a plurality of clock frequencies generated by a second clock generation circuit ( 902 ), the plurality of clock frequencies being different from each other and the selection being based on the change of operating mode to be applied; and

supplying a further clock signal (PCLK) at the selected clock frequency to the island control circuit ( 122 ) to control the timing of the change of the operating mode of the island, wherein:

selecting a first clock frequency for the further clock signal (PCLK) when the change of mode is of a first type; and

selecting a second clock frequency faster or slower than the first clock frequency for the further clock signal (PCLK) when the change of mode is of a second type, the first type of change of mode being longer or shorter to implement that the second type of change of mode.

10. The method of claim 9 , wherein selecting the clock frequency comprises generating a plurality of clock signals (CK_ 1 to CK_N) each at one of the plurality of clock frequencies, and selecting one of the plurality of clock signals to form the further clock signal (PCLK).

11. The method of claim 10 , further comprising generating, by a controller ( 1002 ), a selection signal (F_SEL) for controlling the selection of the further clock signal (PCLK).

12. The method of claim 11 , further comprising generating by the controller ( 1002 ) an enable signal (EN) for selectively activating the generation of an oscillating signal (CK_RO).