Dummy fin structures and methods of forming same
An embodiment method includes depositing a first dielectric film over and along sidewalls of a semiconductor fin, the semiconductor fin extending upwards from a semiconductor substrate. The method further includes depositing a dielectric material over the first dielectric film; recessing the first dielectric film below a top surface of the semiconductor fin to define a dummy fin, the dummy fin comprising an upper portion of the dielectric material; and forming a gate stack over and along sidewalls of the semiconductor fin and the dummy fin.
1. A device comprising:
a first semiconductor fin extending upwards from a semiconductor substrate;
an isolation region around the first semiconductor fin;
an insulating fin extending from above a topmost surface of the isolation region to below the topmost surface of the isolation region, wherein the insulating fin has a different material composition than the isolation region; and
a gate stack disposed over and extending along sidewalls of the first semiconductor fin and over and along sidewalls of the insulating fin.
2. The device of claim 1 , wherein the isolation region comprises silicon oxide, and wherein the insulating fin comprises a first dielectric material, the first dielectric material comprises a carbon containing oxide, a metal containing oxide, or a combination thereof.
3. The device of claim 2 , wherein the insulating fin comprises a second dielectric material disposed between the isolation region and the first dielectric material.
4. The device of claim 3 , wherein the second dielectric material is disposed along sidewalls and under a bottom surface of the first dielectric material.
5. The device of claim 3 , wherein a carbon percentage by weight of the second dielectric material is greater than a carbon percentage by weight of the first dielectric material.
6. The device of claim 3 , wherein a metal percentage by weight of the second dielectric material is greater than a metal percentage by weight of the first dielectric material.
7. The device of claim 2 , wherein the first dielectric material extends continuously from a first sidewall of the isolation region to a second sidewall of the isolation region.
8. The device of claim 2 , wherein the insulating fin further comprises a third dielectric material on a top surface of the first dielectric material.
9. The device of claim 1 further comprising a void between a bottom surface of the insulating fin and a top surface of the isolation region.
10. The device of claim 1 further comprising a semiconductor mesa connecting the first semiconductor fin to a second semiconductor fin, wherein the isolation region further comprises a fourth dielectric material disposed between the isolation region and the semiconductor mesa, and wherein the fourth dielectric material further extends along sidewalls of the semiconductor mesa.
11. The device of claim 1 further comprising a second insulating fin, wherein the second insulating fin is wider than the insulating fin, and the gate stack is disposed over and extends along sidewalls of the second insulating fin.
12. A device comprising:
a first semiconductor fin extending from a substrate to above a first dielectric material;
a second dielectric material extending partially into the first dielectric material, the first dielectric material separates the second dielectric material from the first semiconductor fin, and the second dielectric material extends above the first dielectric material, and a top surface of the first semiconductor fin is level with a top surface of the second dielectric material;
a gate dielectric on a top surface and along sidewalls of the second dielectric material; and
a gate electrode over the gate dielectric.
13. The device of claim 12 further comprising a second semiconductor fin, wherein the first dielectric material extends continuously from the first semiconductor fin to the second semiconductor fin.
14. The device of claim 12 further comprising a third dielectric material along a sidewall and bottom surface of the second dielectric material, wherein the third dielectric material separates the second dielectric material from the first dielectric material.
15. The device of claim 14 , wherein the gate dielectric contacts a top surface of the third dielectric material.
16. The device of claim 12 further comprising a void between a bottom surface of the second dielectric material and the first dielectric material.
17. A device comprising:
a semiconductor fin extending from a substrate to above a first dielectric material;
a second dielectric material extending partially from below a top surface of the first dielectric material to above the top surface of the first dielectric material, the first dielectric material is disposed around the second dielectric material;
a third dielectric material on a top surface of the second dielectric material;
a gate dielectric on a top surface of the third dielectric material, the gate dielectric is further disposed along sidewalls of the second dielectric material, and a portion of the gate dielectric between the semiconductor fin and the second dielectric material extends to a top surface of the first dielectric material; and
a gate electrode over the gate dielectric.
18. The device of claim 17 further comprising a fourth dielectric material on sidewalls and along a bottom surface of the second dielectric material.
19. The device of claim 18 , wherein the fourth dielectric material is disposed along sidewalls of the third dielectric material.
20. The device of claim 17 , wherein a carbon percentage by weight or a metal percentage by weight of the second dielectric material is greater than a respective carbon percentage by weight or metal percentage by weight of the first dielectric material.