Semiconductor package with space efficient lead and die pad design

1. A semiconductor package, comprising:

a die pad comprising a die attach surface, a rear surface opposite the die attach surface, and an outer edge side extending between the die attach surface and the rear surface, the outer edge side having a step-shaped profile wherein an upper section of the die pad laterally overhangs past a lower section of the die pad;

a semiconductor die mounted on the die attach surface and comprising a first electrical terminal on an upper surface of the semiconductor die that faces away from the die attach surface; and

a first conductive clip that directly electrically contacts the first electrical terminal and wraps around the outer edge side of the die pad such that a section of the first conductive clip is at least partially within an area that is directly below the upper section of the die pad and directly laterally adjacent to the lower section.

2. The semiconductor package of claim 1 , further comprising:

an electrically insulating encapsulant that encapsulates the semiconductor die,

wherein the encapsulant comprises a top surface extending over the semiconductor die, a bottom surface opposite from the top surface, and

wherein a lowermost surface of the first conductive clip is at or above a plane of the bottom surface of the encapsulant.

3. The semiconductor package of claim 2 , wherein the lowermost surface of the first conductive clip is a contact surface that extends between an angled bend in the first conductive clip and the outer end of the first conductive clip, wherein the contact surface and the rear surface of the die pad are substantially coplanar with one another, and wherein the contact surface and the bottom surface of the die pad are exposed from the encapsulant.

4. The semiconductor package of claim 3 , wherein the bottom surface of the encapsulant is substantially coplanar with the contact surface and the bottom surface of the die pad.

5. The semiconductor package of claim 2 , wherein the semiconductor die is mounted on the die pad such that the semiconductor die laterally overhangs past the lower section of the die pad, and wherein the outer end of the first conductive clip is disposed directly below the semiconductor die.

6. The semiconductor package of claim 2 , wherein the semiconductor package comprises an intermediary layer disposed between a rear surface of the semiconductor die and the die attach surface, wherein the intermediary layer laterally overhangs past the lower section of the die pad, and wherein the outer end of the first conductive clip is disposed directly below the intermediary layer.

7. The semiconductor package of claim 2 , wherein the semiconductor package further comprises an electrically conductive lead that is spaced apart from the die pad, wherein the semiconductor die further comprises second and third electrical terminals disposed on a lower surface of the semiconductor die that is opposite from the upper surface of the semiconductor die, wherein the second electrical terminal directly electrically contacts the die attach surface, and wherein the third electrical terminal directly electrically contacts an upper surface of the lead.

8. The semiconductor package of claim 2 , wherein the semiconductor die further comprises a second electrical terminal disposed at the upper surface of the semiconductor die, and wherein the semiconductor package further comprises a second conductive clip that directly electrically contacts the second electrical terminal and wraps around the outer edge side of the die pad such that an outer end of the second conductive clip is at least partially within the area that is directly below the upper section of the die pad and directly laterally adjacent to the lower section.

9. The semiconductor package of claim 2 , wherein the first conductive clip comprises a central pad and an elongated finger, wherein the central pad is disposed directly over the first electrical terminal, wherein the elongated finger is narrower than the central pad, wherein the elongated finger connects with the central pad and protrudes out of the encapsulant, and wherein a portion of the elongated finger that is exposed from the encapsulant wraps around the outer edge side of the die pad and extends to the outer end of the first conductive clip.

10. The semiconductor package of claim 9 , wherein the encapsulant completely covers the central pad.

11. The semiconductor package of claim 9 , wherein the central pad extends to the top surface of the encapsulant and comprises an upper surface that is exposed from the encapsulant.

12. The semiconductor package of claim 11 , wherein a thickness of the central pad is greater than a thickness of the elongated finger, the thickness of the central pad being measured between the upper surface of the central pad and a lower surface of the central pad that faces the first electrical terminal, the thickness of the elongated finger being measured between opposite facing upper and lower surfaces that of the elongated finger that connect with the central pad.

13. The semiconductor package of claim 9 , wherein the first conductive clip comprises a plurality of the elongated fingers, wherein each of the elongated fingers are spaced apart from one another and connect to same side of the central pad.

14. A method of packaging a semiconductor device, comprising:

providing a die pad comprising a die attach surface, a rear surface opposite the die attach surface, and an outer edge side extending between the die attach surface and the rear surface, the outer edge side having a step-shaped profile wherein an upper section of the die pad laterally overhangs past a lower section of the die pad;

mounting a semiconductor die on the die attach surface such that a first electrical terminal on an upper surface of the semiconductor die faces away from the die attach surface; and

providing a first conductive clip that directly electrically contacts the first electrical terminal and wraps around the outer edge side of the die pad such that an outer end of the first conductive clip is at least partially within an area that is directly below the upper section of the die pad and directly laterally adjacent to the lower section.

15. The method of claim 14 , further comprising:

forming an electrically insulating encapsulant that encapsulates the semiconductor die,

wherein the encapsulant is formed to comprise a top surface extending over the semiconductor die, a bottom surface opposite from the top surface, and

wherein a lowermost surface of the first conductive clip is at or above a plane of the bottom surface of the encapsulant.

16. The method of claim 15 , wherein providing the first conductive clip comprises:

providing a planar strip of conductive metal that electrically contacts the first terminal;

forming the encapsulant after providing the planar strip of conductive metal such that an exposed portion of the planar strip protrudes out of the encapsulant; and

bending the exposed portion of the planar strip such that the exposed portion wraps around the outer edge side of the die pad such that an outer end of the first conductive clip is at least partially within the area that is directly below the upper section of the die pad and directly laterally adjacent to the lower section.