Apparatus and methods for biasing of power amplifiers
Apparatus and methods for biasing power amplifiers are provided herein. In certain embodiments, a power amplifier includes a bipolar transistor having a base biased by a bias network having a reactance that controls an impedance at the transistor base to achieve substantially flat phase response over large dynamic power levels. For example, the bias network can have a frequency response, such as a high-pass or band-pass response, that reduces the impact of power level on phase distortion (AM/PM).
1. A mobile device comprising:
a transceiver configured to generate a radio frequency input signal;
a front end system including a power amplifier configured to receive the radio frequency input signal and to output a radio frequency output signal, the power amplifier including a power amplifier transistor configured to amplify the radio frequency input signal and a bias network configured to bias an input of the power amplifier transistor with a DC bias voltage, the bias network having a reactance operable to flatten a phase response of the power amplifier, the power amplifier transistor includes a plurality of transistor elements operating in parallel with one another, and the bias network includes a plurality of resistors and a plurality of capacitors, each of the plurality of resistors connected in parallel with a corresponding one of the plurality of capacitors between the DC bias voltage and an input to a corresponding one of the plurality of transistor elements; and
an antenna configured to wirelessly transmit the radio frequency output signal.
2. The mobile device of claim 1 wherein the reactance is operable to track an intrinsic input capacitance of the power amplifier transistor.
3. The mobile device of claim 1 wherein the bias network includes a bias impedance electrically connected between the DC bias voltage and the input of the power amplifier transistor, and a shunt impedance electrically connected between the input of the power amplifier transistor and a reference voltage.
4. The mobile device of claim 3 wherein the bias impedance includes a first resistor, and the shunt impedance includes a second resistor and a capacitor in series.
5. The mobile device of claim 4 wherein the shunt impedance further includes an inductor in series with the second resistor and the capacitor.
6. The mobile device of claim 1 wherein the bias network includes a resistor and a capacitor electrically connected in parallel between the input of the power amplifier transistor and the DC bias voltage.
7. The mobile device of claim 1 wherein the bias network includes a series combination of a capacitor and an inductor electrically connected between the DC bias voltage and the input to the power amplifier transistor, and a resistor in parallel with the series combination of the capacitor and the inductor.
8. The mobile device of claim 1 wherein the power amplifier includes an input stage and an output stage, the power amplifier transistor incorporated in the output stage of the power amplifier.
9. A power amplifier system comprising:
a bias control circuit configured to generate a DC bias voltage; and
a power amplifier configured to receive a radio frequency input signal and to output a radio frequency output signal, the power amplifier including a power amplifier transistor configured to amplify the radio frequency input signal, and a bias network configured to bias an input of the power amplifier transistor with the DC bias voltage, the bias network having a reactance operable to flatten a phase response of the power amplifier, power amplifier transistor includes a plurality of transistor elements operating in parallel with one another, and the bias network includes a plurality of resistors and a plurality of capacitors, each of the plurality of resistors connected in parallel with a corresponding one of the plurality of capacitors between the DC bias voltage and an input to a corresponding one of the plurality of transistor elements.
10. The power amplifier system of claim 9 wherein the reactance is operable to track an intrinsic input capacitance of the power amplifier transistor.
11. The power amplifier system of claim 9 wherein the bias network includes a bias impedance electrically connected between the DC bias voltage and the input of the power amplifier transistor, and a shunt impedance electrically connected between the input of the power amplifier transistor and a reference voltage.
12. The power amplifier system of claim 11 wherein the bias impedance includes a first resistor, and the shunt impedance includes a second resistor and a capacitor in series.
13. The power amplifier system of claim 12 wherein the shunt impedance further includes an inductor in series with the second resistor and the capacitor.
14. The power amplifier system of claim 9 wherein the power amplifier transistor is a bipolar transistor having a base corresponding to the input.
15. The power amplifier system of claim 9 wherein the bias network includes a resistor and a capacitor electrically connected in parallel between the input of the power amplifier transistor and the DC bias voltage.
16. The power amplifier system of claim 9 wherein the bias network includes a series combination of a capacitor and an inductor electrically connected between the DC bias voltage and the input to the power amplifier transistor, and a resistor in parallel with the series combination of the capacitor and the inductor.
17. A method of biasing a power amplifier, the method comprising:
generating a DC bias voltage using a bias control circuit;
receiving a radio frequency input signal as an input to a power amplifier;
amplifying the radio frequency input signal using a power amplifier transistor of the power amplifier; and
biasing an input of the power amplifier transistor with the DC bias voltage using a bias network of the power amplifier, including flattening a phase response of the power amplifier with a reactance of the bias network, the power amplifier transistor includes a plurality of transistor elements operating in parallel with one another, and the bias network includes a plurality of resistors and a plurality of capacitors, each of the plurality of resistors connected in parallel with a corresponding one of the plurality of capacitors between the DC bias voltage and an input to a corresponding one of the plurality of transistor elements.
18. The method of claim 17 further comprising tracking an intrinsic input capacitance of the power amplifier transistor with the reactance of the bias network.
19. The method of claim 17 wherein the bias network includes a bias impedance electrically connected between the DC bias voltage and the input of the power amplifier transistor.
20. The method of claim 19 wherein the bias network includes a shunt impedance electrically connected between the input of the power amplifier transistor and a reference voltage.