Gate driving circuit and display device including the same
A gate driving circuit includes a plurality of stages connected to one another, wherein each of the plurality of stages includes an output unit which outputs a first clock signal as a gate voltage in accordance with a voltage of a Q node and a voltage of a QB node; a first node control unit which controls the voltage of the Q node; and a second node control unit which controls the QB node, wherein the first node control unit includes second and third transistors which discharge the Q node, the second transistor outputs a ground voltage to the Q node in response to a second clock signal, and the third transistor outputs the ground voltage to the Q node in response to the voltage of the QB node.
1. A gate driving circuit, comprising:
a plurality of stages connected to one another, wherein each of the plurality of stages includes:
an output unit which outputs a first clock signal as a gate voltage in accordance with a voltage of a Q node and a voltage of a QB node;
a first node control unit which controls the voltage of the Q node; and
a second node control unit which controls the QB node,
wherein the first node control unit includes second and third transistors which discharge the Q node, the second transistor outputs a ground voltage to the Q node in response to a second clock signal, and the third transistor outputs the ground voltage to the Q node in response to the voltage of the QB node,
wherein all clock signals including the first clock signal and the second clock signal simultaneously rise from a low level to a high level at a reset timing of all frames, and
wherein the plurality of stages are reset at the reset timing of all frames.
2. The gate driving circuit according to claim 1 , wherein the first node control unit further includes a first transistor which charges the Q node.
3. The gate driving circuit according to claim 1 , wherein the voltage of the QB node has a rising timing that coincides with a rising time of the second clock signal.
4. The gate driving circuit according to claim 1 , wherein the second node control unit includes:
a fourth transistor which outputs a power source voltage to the QB node in response to the second clock signal,
a fifth transistor which outputs the ground voltage to the QB node in response to a gate voltage of a previous stage, and
a sixth transistor which outputs the ground voltage to the QB node in response to the voltage of the Q node.
5. The gate driving circuit according to claim 1 , further comprising a protective transistor in which a gate electrode is connected to a power source voltage and source electrode or drain electrode is connected to the Q node.
6. The gate driving circuit according to claim 1 , further comprising a first capacitor in which one of source electrode and drain electrode is connected to the Q node and the other electrode is connected to the ground voltage.
7. The gate driving circuit according to claim 1 , further comprising a second capacitor in which one of source electrode and drain electrode is connected to the QB node and the other electrode is connected to the ground voltage.
8. A display device, comprising:
a display panel including a plurality of pixels;
a gate driving circuit including a plurality of stages sequentially output a gate voltage to the plurality of pixels; and
a timing controller which controls the driving of the gate driving circuit,
wherein each of the plurality of stages includes,
an output unit which outputs a first clock signal as a gate voltage in accordance with a voltage of a Q node and a voltage of a QB node,
a first node control unit which controls the voltage of the Q node, and
a second node control unit which controls the voltage of the QB node,
wherein and the first node control unit includes a second transistor which discharges the Q node in response to a second clock signal and a third transistor which discharges the Q node, in response to the voltage of the QB node, and
wherein all clock signals including the first clock signal and the second clock signal simultaneously rise from a low level to a high level at a reset timing of all frames and
wherein the plurality of stages are reset at the reset timing of all frames.
9. The display device according to claim 8 , wherein the first node control unit further includes a first transistor which charges the Q node.
10. The display device according to claim 8 , wherein the voltage of the QB node has a rising timing that coincides with a rising time of the second clock signal.