Parallel access for memory subarrays
Techniques herein may allow a row of a subarray in a bank of a memory device to be activated before a precharge operation has been completed for a previously opened row of memory cells in the same bank. Each subarray within the bank may be associated with a respective local latching circuit, which may be used to maintain phases at the subarray independent of subsequent commands to the same bank. For example, the latching circuit may internalize timing signals triggered by a precharge command for a first row such that if an activation command is received for a different subarray in the same bank at a time before the precharge operation of the first row is complete, the precharge operation may continue until the first row is closed, as the timing signals triggered by the precharge command may be maintained locally at the subarray using the latching circuit.
1. A method, comprising:
receiving, at a memory device, a first activation command to open a first row of memory cells in a first subarray of a bank;
receiving, at the memory device after receiving the first activation command, a precharge command to close the first row of memory cells;
generating, at the first subarray and based at least in part on receiving the precharge command, a first set of timing signals to close the first row of memory cells;
receiving, at the memory device before the first row of memory cells in the first subarray of the bank is closed, a second activation command to open a second row of memory cells in a second subarray of the bank;
generating, at the second subarray and based at least in part on receiving the second activation command, a second set of timing signals to open the second row of memory cells; and
maintaining, at the first subarray, the first set of timing signals after receiving the second activation command.
2. The method of claim 1 , further comprising:
closing the first row of memory cells, based at least in part on receiving the precharge command, after receiving the second activation command.
3. The method of claim 1 , further comprising:
opening the first row of memory cells based at least in part on the first activation command, wherein the second activation command is received while the first row of memory cells is open.
4. The method of claim 1 , further comprising:
closing the first row of memory cells after receiving the second activation command based at least in part on maintaining the first set of timing signals at the first subarray.
5. The method of claim 4 , wherein maintaining the first set of timing signals at the first subarray after receiving the second activation command comprises:
latching the first set of timing signals within the first subarray after receiving the precharge command.
6. The method of claim 5 , further comprising:
receiving, at the memory device after receiving the second activation command, a second precharge command to close the second row of memory cells; and
maintaining the first set of timing signals after receiving the second precharge command.
7. A method, comprising:
receiving, at a memory device, a first activation command to open a first row of memory cells in a first subarray of a bank;
receiving, at the memory device after receiving the first activation command, a precharge command to close the first row of memory cells;
receiving, at the memory device before the first row of memory cells in the first subarray of the bank is closed, a second activation command to open a second row of memory cells in a second subarray of the bank, wherein the second activation command is received a first amount of time after the precharge command is received;
receiving, at the memory device, a third activation command to open a third row of memory cells in a third subarray of the bank;
receiving, at the memory device, a third precharge command to close the third row of memory cells; and
receiving, at the memory device, a fourth activation command to open a fourth row of memory cells in the third subarray of the bank, wherein the fourth activation command is received a second amount of time after the third precharge command is received, the second amount of time longer than the first amount of time.
8. The method of claim 7 , wherein the first amount of time comprises a shortened row precharge time (tRP_S) and the second amount of time comprises a default row precharge time (tRP).
9. The method of claim 1 , further comprising:
triggering a first set of phase signals at the memory device based at least in part on receiving the first activation command, the first set of phase signals to open the first row of memory cells;
triggering a second set of phase signals at the memory device based at least in part on receiving the precharge command, the second set of phase signals to close the first row of memory cells; and
triggering a third set of phase signals at the memory device based at least in part on receiving the second activation command, the third set of phase signals to open the second row of memory cells.
10. A method, comprising:
receiving, at a memory device, a first activation command to open a first row of memory cells in a first subarray of a bank;
receiving, at the memory device after receiving the first activation command, a precharge command to close the first row of memory cells;
receiving, at the memory device before the first row of memory cells in the first subarray of the bank is closed, a second activation command to open a second row of memory cells in a second subarray of the bank;
triggering a first set of phase signals at the memory device based at least in part on receiving the first activation command, the first set of phase signals to open the first row of memory cells;
triggering a second set of phase signals at the memory device based at least in part on receiving the precharge command, the second set of phase signals to close the first row of memory cells;
triggering a third set of phase signals at the memory device based at least in part on receiving the second activation command, the third set of phase signals to open the second row of memory cells;
opening the first row of memory cells after a first delay following reception of the first activation command, the first delay based at least in part on the first set of phase signals;
closing the first row of memory cells after a second delay following reception of the precharge command, the second delay based at least in part on the second set of phase signals; and
opening the second row of memory cells after a third delay following reception of the second activation command, the third delay based at least in part on the third set of phase signals.