IP Library › Granted Patent US 11,075,120
Granted Patent B2
US 11,075,120 · App. 16/542,578 · Granted Jul 27, 2021

FinFET device and method

Inventors: Kun-Mu Li (Zhudong Township, TW); Heng-Wen Ting (Pingtung, TW); Hsueh-Chang Sung (Zhubei, TW); Yen-Ru Lee (Hsinchu, TW); Chien-Wei Lee (Kaohsiung, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L21/823431H01L21/3065H01L21/3083H01L21/823418H01L21/823481H01L27/0886H01L29/785
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Quick Facts
Patent No.
US 11,075,120
App. No.
16/542,578
Granted
Jul 27, 2021
Kind
B2
Abstract

A device includes a fin over a substrate, the fin including a first end and a second end, wherein the first end of the fin has a convex profile, an isolation region adjacent the fin, a gate structure along sidewalls of the fin and over the top surface of the fin, a gate spacer laterally adjacent the gate structure, and an epitaxial region adjacent the first end of the fin.

Claims (38)

1. A method comprising:

forming a fin over a substrate, the fin comprising a first sidewall and a second sidewall opposite the first sidewall;

forming an isolation region adjacent the fin;

forming a dummy structure over the fin;

forming a gate spacer on a sidewall of the dummy structure;

recessing the fin adjacent the dummy structure to form a first recess using a first etching process;

reshaping the first recess to form a reshaped recess using a second etching process, wherein first regions of the reshaped recess that are adjacent the first sidewall and second regions of the reshaped recess that are adjacent the second sidewall of the fin extend under the gate spacer a first distance, wherein third regions of the reshaped recess that are between the first regions of the reshaped recess and the second regions of the reshaped recess extend under the gate spacer a second distance, wherein the first distance is greater than the second distance; and

epitaxially growing a source/drain region in the reshaped recess.

2. The method of claim 1 , wherein sidewalls of the first recess have a flat profile.

3. The method of claim 1 , wherein the first distance is between 0.1 nm and 5 nm greater than the second distance.

4. The method of claim 1 , wherein the second etching process comprises a plasma etching process using H 2 , HCl, HBr, Cl 2 , CH 4 , C 2 H 4 , or SF 6 as an etchant gas.

5. The method of claim 1 , wherein, after the second etching process, a channel region of the fin has a sidewall with a convex profile.

6. The method of claim 1 , wherein the first recess extends under the gate spacer.

7. The method of claim 1 , wherein portions of the source/drain region grown in the third region of the reshaped recess are farther from the dummy structure than portions of the source/drain region grown in the first region of the reshaped recess.

8. The method of claim 1 , wherein the second etching process etches portions of the fin adjacent the first sidewall of the fin at a greater rate than the second etching process etchings portions of the fin that are between the first sidewall of the fin and the second sidewall of the fin.

9. The method of claim 1 , wherein, after the second etching process, the first regions of the reshaped recess extend under the dummy structure.

10. A method comprising:

patterning a substrate to form a strip, the strip comprising a first semiconductor material;

forming an isolation region along a sidewall of the strip, an upper portion of the strip extending above a top surface of the isolation region;

forming a dummy structure along sidewalls and a top surface of the upper portion of the strip;

performing a first etching process on an portion of the strip to form a recess, the recess exposing a sidewall of a channel region of the strip;

performing a second etching process on the sidewall of the channel region, wherein after the second etching process the sidewall of the channel region has a rounded profile; and

epitaxially growing a source/drain region in the recess.

11. The method of claim 10 , wherein the second etching process etches exposed portions of the channel region that are adjacent the dummy structure at a greater rate than exposed portions of the channel region that are away from the dummy structure.

12. The method of claim 10 , wherein after the first etching process, the sidewall of the channel region is flat.

13. The method of claim 10 , wherein the first etching process comprises a first plasma etching process and wherein the second etching process comprises a second plasma etching process that is different from the first plasma etching process.

14. The method of claim 10 , wherein, after the second etching process, the recess has a concave sidewall.

15. The method of claim 10 , wherein, after the second etching process, the recess extends under the dummy structure.

16. The method of claim 13 , wherein the second plasma etching process comprises etching using H 2 , HCl, HBr, Cl 2 , CH 4 , C 2 H 4 , or SF 6 .

17. A device comprising:

a fin over a substrate, the fin comprising a first end and a second end, wherein the first end of the fin has a convex profile in a plan view;

an isolation region adjacent the fin;

a gate structure along sidewalls of the fin and over the top surface of the fin;

a gate spacer laterally adjacent the gate structure; and

an epitaxial region adjacent the first end of the fin, wherein the first end of the fin protrudes into the epitaxial region.

18. The device of claim 17 , wherein the second end of the fin has a convex profile in a plan view.

19. The device of claim 17 , wherein a first distance between the first end and the second end measured at a sidewall of the fin is between 0.1 nm and 6 nm smaller than a second distance between the first end and the second end measured at the center of the fin.

20. The device of claim 17 , wherein portions of the epitaxial region adjacent the center of the first end of the fin are farther from the gate structure than portions of the epitaxial region adjacent the edges of the first end of the fin.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 3, 2019
From: LI, KUN-MU; SUNG, HSUEH-CHANG; LEE, YEN-RU; LEE, CHIEN-WEI; TING, HENG-WEN
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 050615/0581 →
Continuity (1)
Related Publication 20210050267A1 · Feb 18, 2021