IP Library › Granted Patent US 11,075,185
Granted Patent B2
US 11,075,185 · App. 16/575,006 · Granted Jul 27, 2021

Semiconductor package with multi-level conductive clip for top side cooling

Inventors: Chii Shang Hong (Melaka, MY); Ivan Nikitin (Regensburg, DE); Wei Han Koo (Melaka, MY); Chiew Li Tai (Melaka, MY)
Assignee: Infineon Technologies AG
H01L24/40H01L21/565H01L23/3178H01L23/367H01L24/09
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Quick Facts
Patent No.
US 11,075,185
App. No.
16/575,006
Granted
Jul 27, 2021
Kind
B2
Abstract

A semiconductor package includes a die pad having a die attach surface, a semiconductor die mounted on the die attach surface and having a first bond pad at an upper surface facing away from the die attach surface, an interconnect clip including a first segment which at least partially encloses a central opening, a second segment vertically offset and spaced apart from the first segment, and a support extending between the first segment and the second segment. The package further includes an electrically insulating encapsulant covering the semiconductor die. An upper surface of the first segment of the interconnect clip is exposed from a planar surface of the encapsulant. A lower surface of the second segment is flush against the upper surface of the semiconductor die and conductively connected to the first bond pad.

Claims (41)

1. A semiconductor package, comprising:

a die pad comprising a die attach surface;

a semiconductor die mounted on the die attach surface and comprising a first bond pad and a second bond pad at an upper surface of the semiconductor die facing away from the die attach surface;

an interconnect clip, comprising:

a first segment which at least partially encloses a central opening;

a second segment vertically offset and spaced apart from the first segment; and

a support extending between the first segment and the second segment; and

an electrically insulating encapsulant covering the semiconductor die,

wherein an upper surface of the first segment of the interconnect clip is exposed from a planar surface of the encapsulant,

wherein a lower surface of the second segment is flush against the upper surface of the semiconductor die and conductively connected to the first bond pad, and

wherein from a plan view perspective of the interconnect clip the second bond pad is outside of a footprint of the interconnect clip.

2. The semiconductor package of claim 1 , wherein the second segment is a planar pad with a closed shape geometry, and wherein from a plan view perspective of the interconnect clip, the support wraps around a perimeter of the second segment.

3. The semiconductor package of claim 2 , wherein the second segment has a rectangular geometry, and wherein from the plan view perspective of the interconnect clip, the support wraps around at least one corner of the second segment.

4. The semiconductor package of claim 2 , wherein the support forms a complete enclosed loop extending between the outer edge sides of the second segment and inner edge sides of the first segment which face the central opening.

5. The semiconductor package of claim 1 , wherein from the plan view perspective of the interconnect clip, the interconnect clip has an L-shaped geometry.

6. A method of packaging a semiconductor device, the method comprising:

providing a die pad comprising a die attach surface;

providing a semiconductor die comprising a first bond pad and a second bond pad on an upper surface of the semiconductor die;

mounting the semiconductor die on the die pad such that the first bond pad faces away from the die attach surface;

providing an interconnect clip that comprises:

a first segment which at least partially encloses a central opening;

a second segment vertically offset and spaced apart from the first segment; and

a support extending between the first segment and the second segment;

mounting the interconnect clip on the semiconductor die such that a lower surface of the second segment is flush against the upper surface of the semiconductor die and conductively connected to the first bond pad; and

forming an electrically insulating encapsulant such that the semiconductor die is covered by the encapsulant and such that an upper surface of the first segment of the interconnect clip is exposed from an upper surface of the encapsulant, and

wherein from a plan view perspective of the interconnect clip the second bond pad is outside of a footprint of the interconnect clip.

7. The method of claim 6 , wherein the second segment is a planar pad has a closed shape geometry, and wherein from a plan view perspective of the interconnect clip, the first segment wraps around a perimeter of the second segment.

8. The method of claim 6 , wherein the encapsulant is formed such that the upper surface of the first segment of the interconnect clip is substantially coplanar with the upper surface of the encapsulant, and wherein forming the encapsulant comprises completely covering the interconnect clip with the encapsulant and subsequently planarizing the encapsulant until the upper surface of the first segment is exposed form the planar surface of the encapsulant.

9. The method of claim 6 , wherein from the plan view perspective of the interconnect clip, the interconnect clip has an L-shaped geometry.

10. An interconnect clip, comprising:

a first segment which at least partially encloses a central opening;

a second segment vertically offset and spaced apart from the first segment; and

one or more supports extending between the first segment and the second segment,

wherein from a plan view perspective of the interconnect clip, the interconnect clip has an L-shaped geometry, and

wherein the first segment comprises a first elongated span and a second elongated span that intersects with the first elongated span, and wherein the first elongated span and the second elongated span form an inner corner of an outer edge of the interconnect clip, wherein the central opening meets the inner corner.

11. The interconnect clip of claim 10 , wherein the one or more supports extend diagonally between outer edge sides of the second segment and inner edge sides of the first segment that face the central opening.

12. The interconnect clip of claim 10 , wherein the interconnect clip comprises a plurality of the supports extending between the first segment and the second segment, each of the supports being separated from one another by lateral gaps.

13. The interconnect clip of claim 10 , wherein the interconnect clip includes only one of the supports extending between the first segment and the second segment.

14. The interconnect clip of claim 13 , wherein the second segment is a planar pad with a closed shape geometry, and wherein from a plan view perspective of the interconnect clip, the support wraps around a perimeter of the second segment.

15. The interconnect clip of claim 14 , wherein the second segment has a rectangular geometry, and wherein from the plan view perspective of the interconnect clip, the support wraps around at least one corner of the second segment.

16. The interconnect clip of claim 14 , wherein the support forms a complete enclosed loop extending between the outer edge sides of the second segment and inner edge sides of the first segment which face the central opening.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 25, 2019
From: HONG, CHII SHANG; NIKITIN, IVAN; KOO, WEI HAN; TAI, CHIEW LI
To: INFINEON TECHNOLOGIES AG
Reel/Frame 050490/0407 →
Continuity (2)
Continuation In Part 16402486 · May 3, 2019
Related Publication 20200350272A1 · Nov 5, 2020
Cited By (2)
US 12,506,054 US 12,740,413