IP Library Granted Patent US 11,075,296
Granted Patent B2
US 11,075,296 · App. 16/412,427 · Granted Jul 27, 2021

Trench gate MOSFET and method of manufacturing the same

Inventors: Nobuyuki Shirai (Hsinchu County, TW); Chun-Hsu Chang (Hsinchu County, TW); Ming-Hung Chou (Hsinchu County, TW)
Assignee: uPI Semiconductor Corp.
H01L29/7813H01L21/0332H01L21/0337H01L29/4236H01L29/66734
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Quick Facts
Patent No.
US 11,075,296
App. No.
16/412,427
Granted
Jul 27, 2021
Kind
B2
Abstract

Provided is a method of forming a trench gate MOSFET. A hard mask layer is formed on a substrate. The substrate is partially removed by using the hard mask layer as a mask, so as to form a trench in the substrate. A first insulating layer and a first conductive layer are formed in the lower portion of the trench. A sacrificial layer is formed on the side surface of the upper portion of the trench, and the sacrificial layer is connected to the hard mask layer. An interlayer insulating layer is formed on the first conductive layer by a thermal oxidation process when the sacrificial layer and the hard mask layer are present. A second insulating layer and a second conductive layer are formed in the upper portion of the trench. A trench gate MOSFET is further provided.

Claims (12)

1. A method of manufacturing a trench gate MOSFET, comprising:

forming a hard mask layer on a substrate;

partially removing the substrate by using the hard mask layer as a mask, so as to form a trench in the substrate;

forming a first insulating layer and a first conductive layer in a lower portion of the trench;

forming a sacrificial layer on a sidewall of an upper portion of the trench, wherein the sacrificial layer is connected to the hard mask layer;

forming an interlayer insulating layer on the first conductive layer by a thermal oxidation process when the sacrificial layer and the hard mask layer are present; and

forming a second insulating layer and a second conductive layer in the upper portion of the trench,

wherein after forming the interlayer insulating layer, the trench has a width W1 at a surface of the substrate and a width W2 at a depth of 100-150 nm from the surface of the substrate, and a ratio of W1 to W2 is greater than 1 and less than 1.08.

2. The method of claim 1 , further comprising removing the sacrificial layer and the hard mask layer after forming the interlayer insulating layer.

3. The method of claim 1 , further comprising removing the sacrificial layer and a portion of the hard mask layer after forming the interlayer insulating layer.

4. The method of claim 3 , wherein a material of the remaining hard mask layer comprises sillicon nitride or sillicon oxynitride after removing the portion of the hard mask layer.

5. The method of claim 1 , wherein the hard mask layer is a multi-layer composite structure, and a material of the sacrificial layer is the same as a material of one layer of the hard mask layer.

Assignments (2)
MERGER Recorded Jul 3, 2019
From: UBIQ SEMICONDUCTOR CORP.
To: UPI SEMICONDUCTOR CORP.
Reel/Frame 049672/0903 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 15, 2019
From: SHIRAI, NOBUYUKI; CHANG, CHUN-HSU; CHOU, MING-HUNG
To: UPI SEMICONDUCTOR CORP.
Reel/Frame 049178/0563 →
Priority Claims (1)
TW 107116645 · May 16, 2018 · national
Continuity (1)
Related Publication 20190355846A1 · Nov 21, 2019