Reduced-complexity integrated guaranteed-rate optical packet switch

1. A method of operating a plurality of switches within a packet-switched network that delivers Guaranteed-Rate (GR) traffic flows, each of said plurality of switches comprising:

N input ports;

M output ports;

N×M queues, wherein each of said N input ports is associated with M of said N×M queues and each of said M output ports is associated with N of said N×M queues, and wherein each of said N×M queues buffers data which belongs to those of said GR traffic flows which arrive at a particular one of said N input ports and which depart from a particular one of said M output ports, and wherein each of said N*M queues is associated with a guaranteed data-rate;

a first memory,

said method comprising:

for each switch of said plurality of switches,

determining a first periodic schedule that identifies which of said N×M queues, if any, has reservations to receive and buffer data, for a plurality of time-intervals within a scheduling-interval;

storing said first periodic schedule in said first memory of said switch;

wherein for each queue of said N×M queues, said first periodic schedule reserves a sufficient amount of time for receiving data in said scheduling-interval to meet the guaranteed data-rate requirement of said N×M queue;

and wherein for each queue of said N×M queues, said first periodic schedule reserves a substantially-equal amount of time for receiving data in each half of said scheduling-interval.

2. The method of claim 1 , wherein each switch of said plurality of switches further comprises a second memory;

said method further comprising:

for each switch of said plurality of switches,

determining a second periodic schedule that identifies which of said N×M queues, if any, has reservations to transmit data, for a plurality of time-intervals within said scheduling-interval;

storing said second periodic schedule in said second memory of said switch;

wherein for each queue of said N×M queues, said second periodic schedule reserves a sufficient amount of time for transmitting data in said scheduling-interval to meet the guaranteed data-rate requirement of said N×M queue;

and wherein for each queue of said N×M queues, said second periodic schedule reserves a substantially-equal amount of time for transmitting data in each half of said scheduling-interval.

3. The method of claim 2 , wherein for each switch of said plurality of switches, said first memory is distributed over the input ports of said switch.

4. The method of claim 2 , wherein each of said time-intervals represents a time-slot with a fixed duration of time, and said scheduling-interval represents a scheduling-frame with a fixed number of time-slots.

5. The method of claim 3 , wherein each of said time-intervals represents a time-slot with a fixed duration of time, and said scheduling-interval represents a scheduling-frame with a fixed number of time-slots.

6. A deterministic packet switch for switching a plurality of guaranteed-rate (GR) traffic flows over a set of output ports, without processing packet headers, wherein each GR traffic flow is associated with a guaranteed data-rate, comprising:

N input ports, each comprising a data-receiver;

M output ports, each comprising a data-transmitter;

N×M queues, wherein each of said N input ports is associated with M of said N×M queues and each of said M output ports is associated with N of said N×M queues, wherein each of said N×M queues buffers data which belongs to those of said GR traffic flows which arrive at a particular one of said N input ports and which depart from a particular one of said M output ports, and wherein each of said N×M queues is associated with a guaranteed data-rate;

a first memory for storing a first periodic schedule;

a controller operable to receive control packets from a network control-plane;

wherein said first periodic schedule specifies which of said N*M queues, if any, has reservations to receive and buffer data for a plurality of time-intervals in a scheduling-interval;

wherein for each of said N×M queues, said first periodic schedule reserves a sufficient amount of time for receiving data in said scheduling-interval to satisfy the guaranteed data-rate requirement of said N×M queue;

wherein for each of said N×M queues, said first periodic schedule reserves a substantially-equal amount of time for receiving data in each half of said scheduling-interval;

and wherein said controller can configure said first memory with said first periodic schedule.

7. The deterministic packet switch of claim 6 , further comprising;

a second memory for storing a second periodic schedule;

wherein said second periodic schedule specifies which of said N*M queues, if any, has reservations to transmit data for a plurality of time-intervals in said scheduling-interval;

and wherein for each of said N×M queues, said second periodic schedule reserves a sufficient amount of time for transmitting data in said scheduling-interval to satisfy the guaranteed data-rate requirement of said N×M queue.

8. The deterministic packet switch of claim 7 , wherein for each of said N×M queues, said second periodic schedule reserves a substantially-equal amount of time for transmitting data in each half of said scheduling-interval.

9. The deterministic packet switch of claim 7 , wherein for each of said N×M queues, said first periodic schedule reserves a substantially-equal amount of time for receiving data in each quarter of said scheduling-interval, and said second periodic schedule reserves a substantially-equal amount of time for transmitting data in each quarter of said scheduling-interval.

10. The deterministic packet switch of claim 9 , wherein said first memory is distributed over the input ports of said switch.

11. The deterministic packet switch of claim 10 , wherein said second memory is distributed over several smaller memories throughout said switch.

12. The deterministic packet switch of claim 9 , wherein each of said plurality of time-intervals represents a time-slot with a fixed duration of time, and wherein said scheduling-interval represents a scheduling-frame with a fixed number of time-slots.

13. The deterministic packet switch of claim 9 , wherein each of said N×M queues comprises a plurality of sub-queues.

14. The deterministic packet switch of claim 13 , wherein for each of said N×M queues, each of said plurality of sub-queues is associated with a guaranteed data-rate.

15. The deterministic packet switch of claim 14 , wherein at least one of said plurality of sub-queues buffers data which belongs to one GR traffic flow.

16. The deterministic packet switch of claim 14 , wherein at least one of said plurality of sub-queues buffers data which belongs to a plurality of GR traffic flows.

17. The deterministic packet switch of claim 16 , wherein said plurality of GR traffic flows belong to the same traffic class.

18. The deterministic packet switch of claim 9 , further comprising a second controller, wherein said second controller will select data to transmit from a sub-queue using a ‘First Come First Served’ (FCFS) scheduling policy.

19. The deterministic packet switch of claim 14 , further comprising: a third memory for storing a third periodic schedule, wherein said third periodic schedule specifies which of said sub-queues, if any, associated with each of said N×M queues, if any, has reservations to receive data, for a plurality of time-intervals in said scheduling-interval; a fourth memory for storing a fourth periodic schedule, wherein said fourth periodic schedule specifies which of said sub-queues, if any, associated with each of said N×M queues, if any, has reservations to transmit data, for a plurality of time-intervals in said scheduling-interval;

wherein for each of said N×M queues, and for each of said sub-queues associated with said N×M queue, said third periodic schedule reserves for each of said sub-queues a sufficient amount of time for receiving data in said scheduling-interval to meet the guaranteed data-rate requirement of said sub-queue; wherein for each of said N×M queues, and for each of said sub-queues associated with said N×M queue, said fourth periodic schedule reserves a sufficient amount of time for transmitting data in said scheduling-interval to meet the guaranteed data-rate requirement of said sub-queue; and wherein said controller can configure each of said third and fourth memories with its associated schedule.

20. The switch of claim 19 , wherein each of said plurality of time-intervals represents a time-slot with a fixed duration of time, and said scheduling-interval represents a scheduling-frame comprising a fixed number of time-slots.

21. The switch of claim 12 ,

wherein said controller receives from said control-plane a traffic rate matrix with N×M elements, which specify the guaranteed data-rates to be supported by said N×M queues, wherein each guaranteed data-rate is expressed as a number of time-slot reservations per scheduling-frame with F time-slots;

and wherein said controller computes the first periodic schedule and second periodic schedule from said traffic rate matrix.

22. The switch of claim 19 ,

wherein said controller receives from said control-plane the guaranteed data-rates associated with each of the GR traffic flows which traverse said switch, wherein each guaranteed data-rate is expressed as a number of time-slot reservations per scheduling-frame with F time-slots;

and wherein said controller computes said third periodic schedule and said fourth periodic schedule.

23. The switch of claim 9 , packaged into a single integrated circuit package.

24. The switch of claim 23 , packaged into a single Ball Grid Array (BGA) package.

25. The switch of claim 23 , wherein the integrated circuit package comprises multiple integrated circuit die.

26. The switch of claim 25 , wherein each of said N input ports comprises an optical-to-electronic (OE) data-receiver that converts received optical signals to electrical signals, and wherein each output port comprises an electrical-to-optical (EO) data-transmitter that converts received electrical signals to optical signals.

27. The switch of claim 26 , wherein said OE data-receivers are realized using the Silicon Photonics technology, and wherein said EO data-transmitters are realized using the Silicon Photonics technology.

28. The switch of claim 9 , further comprising a security-controller that monitors data that arrives at each of said N×M queues, and detects the arrival of unauthorized data.

29. The switch of claim 28 , wherein unauthorized data arrives at one of said N×M queues at a time-interval for which no arrival has been scheduled in said first periodic schedule for said queue.

30. The switch of claim 28 , wherein unauthorized data arrives at one of said N×M queues when the amount of data that arrives for said queue in said scheduling-interval exceeds the amount of data that should arrive for said queue in said scheduling-interval according to the guaranteed data-rate for said queue.

31. The switch of claim 19 , further comprising a security-controller that monitors data that arrives, and detects the arrival of unauthorized data.

32. The switch of claim 31 , wherein said security-controller monitors data that arrives at each of said sub-queues, and detects the arrival of unauthorized data, and wherein unauthorized data arrives at one of said sub-queues at a time-interval for which no arrival has been scheduled in said third periodic schedule for said sub-queue.

33. The switch of claim 31 , wherein said security-controller detects the arrival of unauthorized data which occurs when the amount of data that arrives at one of said sub-queues in said scheduling-interval exceeds the amount of data that should arrive for said sub-queue in said scheduling-interval according to the guaranteed data-rate for said sub-queue.

34. The switch of claim 12 , further comprising a security-controller that monitors data that arrives at each of said N×M queues, and detects the arrival of unauthorized data, wherein unauthorized data arrives at one of said N×M queues at a time-slot for which no arrival has been scheduled in said first periodic schedule for said queue.

35. The switch of claim 20 , further comprising a security-controller that monitors data that arrives, and detects the arrival of unauthorized data.

36. The switch of claim 35 , wherein said security-controller monitors data that arrives at each of said sub-queues, and detects the arrival of unauthorized data, and wherein unauthorized data arrives at one of said sub-queues at a time-slot for which no arrival has been scheduled in said third periodic schedule for that sub-queue.

37. The switch of claim 12 , wherein each of said GR traffic flows transmits Internet Protocol (IP) packets;

wherein the reception of a large IP packet may require multiple time-slots, and wherein the transmission of a large IP packet may require multiple time-slots.

38. The switch of claim 37 , wherein the reception of a large IP packet may require multiple consecutive time-slots, and wherein the transmission of a large IP packet may require multiple consecutive time-slots.