RF integrated power condition capacitor
The present invention includes a method of fabricating an integrated RF power condition capacitor with a capacitance greater than or equal to 1 of and less than 1 mm 2 , and a device made by the method.
1. A method of making an integrated large capacitance in a small form factor for power conditioning on a photodefinable glass comprising:
depositing a conductive seed layer on a photodefinable glass processed to form one or more via openings in the photodefinable glass;
placing the photodefinable glass substrate with a metallized seed layer electroplating metal to fill one or more openings in the photodefinable glass substrate to form vias;
chemically-mechanically polishing a front and a back surface of the photodefinable glass substrate to leave only the filled vias;
exposing and converting at least one rectangular portion of the photosensitive glass substrate around two adjacent filled vias;
etching the rectangular portion exposing at least one pair of adjacent filled vias to form metal posts;
flash coating a non-oxidizing layer on the metal posts that form a first electrode;
depositing a dielectric layer on or around the posts;
metal coating the dielectric layer to form a second electrode;
connecting a first metal layer to all of the first electrodes in parallel to form an inner electrode for a capacitor; and
connecting a second metal layer to all of the second electrodes in parallel to form an outer electrode for the capacitor.
2. The method of claim 1 , wherein the dielectric layer is a thin film between 0.5 nm and 1000 nm thick.
3. The method of claim 1 , wherein the dielectric layer is a sintered paste between 0.05 μm and 100 μm thick.
4. The method of claim 1 , wherein the dielectric layer has an electrical permittivity between 10 and 10,000.
5. The method of claim 1 , wherein the dielectric layer has an electrical permittivity between 2 and 100.
6. The method of claim 1 , wherein the dielectric layer is deposited by ALD.
7. The method of claim 1 , wherein the dielectric layer is deposited by doctor blading.
8. The method of claim 1 , wherein the capacitor has a capacitance density greater than 1,000 pf/mm 2 .
9. A method of making an integrated large capacitance in a small form factor for power conditioning on a photodefinable glass substrate comprising:
masking a circular pattern on the photosensitive glass substrate; exposing at least one portion of the photosensitive glass substrate to an activating UV energy source;
heating the photosensitive glass substrate to a heating phase of at least ten minutes above its glass transition temperature;
cooling the photosensitive glass substrate to transform at least part of the exposed glass to a crystalline material to form a glass—ceramic crystalline substrate;
partially etching away the ceramic phase of the photodefinable glass substrate with an etchant solution;
depositing a conductive seed layer on the photodefinable glass;
placing the photodefinable glass substrate with a metallized seed layer electroplating metal to fill one or more openings in the photodefinable glass substrate to form vias;
chemically-mechanically polishing a front and a back surface of the photodefinable glass substrate to leave only the filled vias;
exposing and converting at least one rectangular portion of the photosensitive glass substrate around two adjacent filled vias;
etching the rectangular portion exposing at least one pair of adjacent filled vias to form metal posts;
flash coating a non-oxidizing layer on the metal posts that form a first electrode;
depositing a dielectric layer on or around the posts;
metal coating the dielectric layer to form a second electrode;
connecting a first metal layer to all of the first electrodes in parallel to form an inner electrode for a capacitor; and
connecting a second metal layer to all of the second electrodes in parallel to form an outer electrode for the capacitor.
10. The method of claim 9 , wherein the dielectric layer is a thin film between 0.5 nm and 100 nm thick.
11. The method of claim 9 , wherein the dielectric layer is a sintered paste between 0.05 μm and 100 μm thick.
12. The method of claim 9 , wherein the dielectric layer has an electrical permittivity between 10 and 10,000.
13. The method of claim 9 , wherein the dielectric layer has an electrical permittivity between 2 and 100.
14. The method of claim 9 , wherein the dielectric layer is deposited by ALD.
15. The method of claim 9 , wherein the dielectric layer is deposited by doctor blading.
16. The method of claim 9 , wherein the capacitor has a capacitance density greater than 1,000 pf/mm 2 .
17. An integrated capacitor made by a method comprising:
masking a circular pattern on a photosensitive glass substrate;
exposing at least one portion of the photosensitive glass substrate to an activating UV energy source;
heating the photosensitive glass substrate to a heating phase of at least ten minutes above its glass transition temperature;
cooling the photosensitive glass substrate to transform at least part of the exposed glass to a crystalline material to form a glass—ceramic crystalline substrate;
partially etching away the ceramic phase of the photodefinable glass substrate with an etchant solution;
depositing a conductive seed layer on the photodefinable glass; placing the photodefinable glass substrate with a metallized seed layer electroplating metal to fill one or more openings in the photodefinable glass substrate to form vias;
chemically-mechanically polishing a front and a back surface of the photodefinable glass substrate to leave only the filled vias;
exposing and converting at least one rectangular portion of the photosensitive glass substrate around two adjacent filled vias;
etching the rectangular portion exposing at least one pair of adjacent filled vias to form metal posts;
flash coating a non-oxidizing layer on the metal posts that form a first electrode;
depositing a dielectric layer on or around the posts;
metal coating the dielectric layer to form a second electrode;
connecting a first metal layer to all of the first electrodes in parallel to form an inner electrode for a capacitor; and
connecting a second metal layer to all of the second electrodes in parallel to form an outer electrode for the capacitor.
18. The capacitor of claim 17 , wherein the dielectric layer is a thin film between 0.5 nm and 1000 nm thick.
19. The capacitor of claim 17 , wherein the dielectric layer is a sintered paste between 0.05 μm and 100 μm thick.
20. The capacitor of claim 17 , wherein the dielectric material has an electrical permittivity between 10 and 10,000.
21. The capacitor of claim 17 , wherein the dielectric thin film has an electrical permittivity between 2 and 100.
22. The capacitor of claim 17 , wherein the dielectric thin film material is deposited by ALD.
23. The capacitor of claim 17 , wherein the dielectric paste material is deposited by doctor blading.
24. The capacitor of claim 17 , wherein the capacitor has a capacitance density greater than 1,000 pf/mm 2 .