IP Library › Granted Patent US 11,080,186
Granted Patent B2
US 11,080,186 · App. 16/547,410 · Granted Aug 3, 2021

Storage device and storage system

Inventors: Kwang-Kyu Bang (Hwaseong-si, KR); Young-Min Kim (Seongnam-si, KR); Kwan-Bin Yim (Hwaseong-si, KR)
Assignee: Samsung Electronics Co., Ltd.
G06F12/0804G06F3/0619G06F3/0653G06F3/0659G06F3/0689G06F2212/1032
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Quick Facts
Patent No.
US 11,080,186
App. No.
16/547,410
Granted
Aug 3, 2021
Kind
B2
Abstract

Provided is a storage device including a power management integrated circuit chip; multiple non-volatile memories configured to receive power from the power management integrated circuit chip; and a controller configured to control the non-volatile memories, wherein the controller checks a state of the power during a read operation and a write operation on the non-volatile memories and, when a power failure is detected in at least one of the non-volatile memories, implements a power failure detection mode regarding the read operation and the write operation on all of the non-volatile memories.

Claims (42)

1. A storage device, comprising:

a power management integrated circuit chip;

a plurality of non-volatile memories configured to receive power from the power management integrated circuit chip; and

a controller configured to control the non-volatile memories,

wherein the controller checks a state of the power during a read operation and a write operation on the non-volatile memories and, when a power failure is detected in at least one of the non-volatile memories, implements a power failure detection mode regarding the read operation and the write operation on all of the non-volatile memories,

wherein the controller detects power failure when a read voltage and a write voltage provided to the non-volatile memories are temporarily interrupted, transmits an alarm signal to a host when power failure is detected in at least one of the non-volatile memories, and transmits an alarm cancellation signal to the host when power failure is not detected in all of the non-volatile memories after the alarm signal is transmitted.

2. The storage device of claim 1 , wherein, in the power failure detection mode regarding the read operation, an attempt to read a first page is retried, and,

in the power failure detection mode regarding the write operation, a write is allocated to a next free block.

3. The storage device of claim 1 , wherein the read operation and the write operation are performed when power failure is not detected in all of the non-volatile memories.

4. The storage device of claim 1 , wherein the controller is configured as a one-body package with the non-volatile memories.

5. The storage device of claim 1 , wherein the non-volatile memories constitute a redundant array of independent disks.

6. A storage system, comprising:

a plurality of storage devices each comprising a power management integrated circuit chip, a non-volatile memory receiving power from the power management integrated circuit chip, and a controller configured to control the non-volatile memory; and

a host configuring a multiple interface communication with the storage devices,

wherein the host checks a state of the power during a read operation and a write operation on the non-volatile memories included in the storage devices and, when a power failure is detected in at least one of the non-volatile memories, implements a power failure detection mode regarding the read operation and the write operation on all of the non-volatile memories,

wherein the host selects some of the storage devices as a selected plurality of storage devices by controlling a channel of the multiple interface communication, and

checks the state of the power regarding the non-volatile memory of each of the selected plurality of storage devices.

7. The storage system of claim 6 , wherein, in the power failure detection mode regarding the read operation, an attempt to read a first page is retried, and,

in the power failure detection mode regarding the write operation, a write is allocated to a next free block.

8. The storage system of claim 6 , wherein the host directly transmits and receives the state of the power to and from the power management integrated circuit chip and transmits and receives the state of the power to and from the controller of each of the selected plurality of storage devices using a bypass.

9. The storage system of claim 6 ,

wherein the host directly transmits and receives the state of the power to and from the power management integrated circuit chip and the controller of each of the selected plurality of storage devices.

10. The storage system of claim 9 , wherein the channel comprises:

a first channel through which the host and the power management integrated circuit chip communicate; and

a second channel through which the host and the controller of each of the selected plurality of storage devices communicate, and

the first channel and the second channel have different interfaces.

11. The storage system of claim 6 , wherein an alarm signal is transmitted to a host when power failure is detected in at least one of the storage devices, and

an alarm cancellation signal is transmitted to the host when power failure is not detected in all of the storage devices after the alarm signal is transmitted.

12. The storage system of claim 11 , wherein the host analyzes the alarm signal and the alarm cancellation signal and determines whether a failure in the storage devices exists.

13. The storage system of claim 6 , wherein the storage devices are M.2 type solid state drives, and

the storage devices are consecutively arranged.

14. A storage system, comprising:

a plurality of storage devices each comprising a power management integrated circuit chip, a non-volatile memory receiving power from the power management integrated circuit chip, and a controller configured to control the non-volatile memory;

a contact module capable of mounting the storage devices; and

a host configured to communicate with the storage devices,

wherein the host switches a state of the power to a test mode while a read operation and a write operation are being performed on non-volatile memories included in the storage devices and collects information regarding whether to implement a power failure detection mode regarding the read operation and the write operation on the non-volatile memories.

15. The storage system of claim 14 , wherein the power failure detection mode is implemented by a program code stored in each of the plurality of storage devices,

in the power failure detection mode regarding the read operation, an attempt to read a first page is retried, and,

in the power failure detection mode regarding the write operation, a write is allocated to a next free block.

16. The storage system of claim 14 , wherein, in the test mode, abnormal power with which a read operation and a write operation are not performed is provided.

17. The storage system of claim 14 , further comprising: a monitoring device configured to check the storage devices,

wherein the monitoring device determines a failure of the storage devices by checking the information collected by the host.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 22, 2019
From: BANG, KWANG-KYU; KIM, YOUNG-MIN; YIM, KWAN-BIN
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 050128/0396 →
Priority Claims (1)
KR 10-2018-0166414 · Dec 20, 2018 · national
Continuity (1)
Related Publication 20200201762A1 · Jun 25, 2020