Lazy increment for high frequency counters
A computing apparatus, including: a processor; a pointer to a counter memory location; and a lazy increment counter engine to: receive a stimulus to update the counter; and lazy increment the counter including issuing a weakly-ordered increment directive to the pointer.
1. A computing apparatus, comprising:
a processor;
instructions to allocate a pointer to a counter memory location; and
an engine to:
receive a stimulus to update a counter; and
increment the counter comprising issuing a non-cache coherent increment directive to the pointer.
2. The computing apparatus of claim 1 , wherein the counter memory location is mapped to a counter buffer of a counter device.
3. The computing apparatus of claim 1 , wherein the non-cache coherent increment directive is a cache bypass write directive.
4. The computing apparatus of claim 3 , further comprising a write combining buffer (WCB).
5. The computing apparatus of claim 4 , wherein the write directive is a write combining (WC) directive via the WCB.
6. The computing apparatus of claim 3 , wherein the write directive is an uncacheable (UC) write.
7. The computing apparatus of claim 3 , wherein the write directive is to write a 64-bit counter payload to the counter memory location.
8. The computing apparatus of claim 7 , wherein the counter payload comprises a 56-bit counter value and an 8-bit operation type.
9. The computing apparatus of claim 1 , wherein lazy incrementing the counter comprises issuing a fast doorbell write operation.
10. The computing apparatus of claim 1 , wherein lazy incrementing the counter comprises write combining with fencing.
11. The computing apparatus of claim 1 , wherein lazy incrementing the counter comprises a local writeback counter with write combining.
12. One or more tangible, non-transitory storage mediums including instructions for providing an engine to:
receive a stimulus to update a counter; and
increment the counter comprising issuing a non-cache coherent increment directive to a pointer.
13. The one or more tangible, non-transitory storage mediums of claim 12 , wherein a counter memory location is mapped to a counter buffer of a counter device.
14. The one or more tangible, non-transitory storage mediums of claim 13 , wherein the non-cache coherent increment directive is a cache bypass write directive.
15. The one or more tangible, non-transitory storage mediums of claim 14 , further comprising a write combining buffer (WCB).
16. The one or more tangible, non-transitory storage mediums of claim 15 , wherein the write directive is a write combining (WC) directive via the WCB.
17. The one or more tangible, non-transitory storage mediums of claim 14 , wherein the write directive is an uncacheable (UC) write.
18. The one or more tangible, non-transitory storage mediums of claim 14 , wherein the write directive is to write a 64-bit counter payload to the counter memory location.
19. The one or more tangible, non-transitory storage mediums of claim 18 , wherein the counter payload comprises a 56-bit counter value and an 8-bit operation type.
20. The one or more tangible, non-transitory storage mediums of claim 12 , wherein lazy incrementing the counter comprises issuing a fast doorbell write operation.
21. The one or more tangible, non-transitory storage mediums of claim 12 , wherein lazy incrementing the counter comprises write combining with fencing.
22. The one or more tangible, non-transitory storage mediums of claim 12 , wherein lazy incrementing the counter comprises a local writeback counter with write combining.
23. A computer-implemented method of lazy incrementing a counter, comprising:
allocating a pointer to a counter memory location;
receiving a stimulus to update the counter; and
incrementing the counter comprising issuing a non-cache coherent increment directive to the pointer.
24. The method of claim 23 , wherein the counter memory location is mapped to a counter buffer of a counter device.
25. The method of claim 23 , wherein the non-cache coherent increment directive is a cache bypass write directive.