Shift register and method of driving the same, gate driving circuit, display device

1. A shift register, comprising:

a display sub-shift register; and

a detection sub-shift register coupled to the display sub-shift register, the detection sub-shift register comprising:

a first input terminal, a first output terminal, a first reset terminal, and a second reset terminal;

a detection input sub-circuit coupled to a first clock signal terminal, a second clock signal terminal, the first input terminal, a pull-up control node and a first pull-up node of the detection sub-shift register, and configured to provide a signal of the first input terminal to the pull-up control node under control of the first clock signal terminal, and provide a signal of the second clock signal terminal to the first pull-up node under control of the pull-up control node;

a detection output sub-circuit coupled to the first pull-up node, a third clock signal terminal and the first output terminal, and configured to provide a signal of the third clock signal terminal to the first output terminal under control of the first pull-up node;

a detection output control sub-circuit coupled to the first output terminal, a first pull-down node and a low-level voltage terminal, and configured to provide a signal of the low-level voltage terminal having a constant low level to the first output terminal under control of the first pull-down node;

a detection reset sub-circuit coupled to the first reset terminal, the second reset terminal, the first pull-up node, the pull-up control node and the low-level voltage terminal, and configured to provide the signal of the low-level voltage terminal to the first pull-up node under control of the first reset terminal, and provide the signal of the low-level voltage terminal to the pull-up control node under control of the second reset terminal; and

a detection node control sub-circuit coupled to a first control terminal, a second control terminal, the first pull-up node, the first pull-down node, and the low-level voltage terminal, and configured to provide the signal of the low-level voltage terminal to the first pull-down node under control of the first control terminal, the second control terminal, and the first pull-up node.

2. The shift register of claim 1 , wherein a time period in which a signal of the first pull-up node is at an on level at least partially overlaps with a time period in which a signal of the first output terminal is at an on level, and when the signal of the first pull-up node is at an off level, the signal of the first output terminal is at an off level.

3. The shift register of claim 1 , wherein the detection sub-shift register further comprises:

a first control sub-circuit coupled to a display control terminal, the first pull-down node, and the low-level voltage terminal, and configured to provide the signal of the low-level voltage terminal to the first pull-down node under control of the display control terminal.

4. The shift register of claim 1 , wherein a voltage level of an off signal provided to the first reset terminal, the second reset terminal, and the first clock signal terminal is lower than a voltage level of the signal of the low-level voltage terminal.

5. The shift register of claim 1 , wherein the detection output sub-circuit is further coupled to a fourth clock signal terminal and a second output terminal, and is configured to provide a signal of the fourth clock signal terminal to the second output terminal under control of the first pull-up node, and

the detection output control sub-circuit is further coupled to the second output terminal, and is configured to provide the signal of the low-level voltage terminal to the second output terminal under control of the first pull-down node.

6. The shift register of claim 1 , wherein the detection input sub-circuit comprises: a first transistor and a third transistor, and wherein

the first transistor has a control electrode coupled to the first clock signal terminal, a first electrode coupled to the first input terminal, and a second electrode coupled to the pull-up control node, and

the third transistor has a control electrode coupled to the pull-up control node, a first electrode coupled to the second clock signal terminal, and a second electrode coupled to the first pull-up node.

7. The shift register of claim 1 , wherein the detection input sub-circuit comprises: a first transistor, a third transistor, and a twelfth transistor, and wherein

the first transistor has a control electrode coupled to the first clock signal terminal, a first electrode coupled to the first input terminal, and a second electrode coupled to a first electrode of the twelfth transistor,

the twelfth transistor has a control electrode coupled to the first clock signal terminal, and a second electrode coupled to the pull-up control node, and

the third transistor has a control electrode coupled to the pull-up control node, a first electrode coupled to the second clock signal terminal, and a second electrode coupled to the first pull-up node.

8. The shift register of claim 6 , wherein the detection reset sub-circuit comprises a first reset sub-circuit and a second reset sub-circuit,

the first reset sub-circuit is coupled to the first pull-up node, the low-level voltage terminal, and the first reset terminal, and configured to provide the signal of the low-level voltage terminal to the first pull-up node under control of the first reset terminal, and

the second reset sub-circuit is coupled to the second reset terminal, the pull-up control node and the low-level voltage terminal, and configured to provide the signal of the low-level voltage terminal to the pull-up control node under control of the second reset terminal.

9. The shift register of claim 8 , wherein the first reset sub-circuit comprises a fourth transistor, and

the fourth transistor has a control electrode coupled to the first reset terminal, a first electrode coupled to the first pull-up node, and a second electrode coupled to the low-level voltage terminal.

10. The shift register of claim 8 , wherein the first reset sub-circuit comprises: a fourth transistor and a fifteenth transistor,

the fourth transistor has a control electrode coupled to the first reset terminal, a first electrode coupled to the first pull-up node, and a second electrode coupled to a first feedback node, and

the fifteenth transistor has a control electrode coupled to the first reset terminal, a first electrode coupled to the first feedback node, and a second electrode coupled to the low-level voltage terminal,

the detection sub-shift register further comprises a first leakage prevention sub-circuit,

the first leakage prevention sub-circuit is coupled to the first pull-up node, the first pull-down node, the first feedback node, a high-level voltage terminal, and the low-level voltage terminal, and configured to, under control of the first pull-down node and the first pull-up node, provide the signal of the low-level voltage terminal to the first feedback node in response to the first pull-down node being at an on level, and provide a signal of the high-level voltage terminal to the first feedback node in response to the first pull-up node being at an on level and the first pull-down node being at an off level, to maintain the on level of the first pull-up node, and

the first leakage prevention sub-circuit comprises a sixteenth transistor, a seventeenth transistor, and an eighteenth transistor,

the sixteenth transistor has a control electrode coupled to the first pull-down node, a first electrode coupled to the first pull-up node, and a second electrode coupled to a first electrode of the seventeenth transistor,

the seventeenth transistor has a control electrode coupled to the first pull-down node, and a second electrode coupled to the low-level voltage terminal,

the eighteenth transistor has a control electrode coupled to the first pull-up node, a first electrode coupled to the second electrode of the sixteenth transistor, and a second electrode coupled to the high-level voltage terminal, and

the first feedback node is coupled to the first electrode of the eighteenth transistor.

11. The shift register of claim 8 , wherein the second reset sub-circuit comprises a second transistor, and

the second transistor has a control electrode coupled to the second reset terminal, a first electrode coupled to the pull-up control node, and a second electrode coupled to the low-level voltage terminal.

12. The shift register of claim 8 , wherein the second reset sub-circuit comprises a second transistor and a thirteenth transistor,

the second transistor has a control electrode coupled to the second reset terminal, a first electrode coupled to the pull-up control node, and a second electrode coupled to a second feedback node, and

the thirteenth transistor has a control electrode coupled to the second reset terminal, a first electrode coupled to the second feedback node, and a second electrode coupled to the low-level voltage terminal,

the detection sub-shift register further comprises a second leakage prevention electronic circuit,

the second leakage prevention sub-circuit is coupled to the pull-up control node, a high-level voltage terminal and the second feedback node, and configured to provide the signal of the high-level voltage terminal to the second feedback node under control of the pull-up control node, to maintain the on level of the pull-up control node, and

the second leakage prevention sub-circuit comprises a fourteenth transistor,

the fourteenth transistor has a control electrode coupled to the pull-up control node, a first electrode coupled to the high-level voltage terminal, and a second electrode coupled to the second feedback node.

13. The shift register of claim 7 , wherein the detection reset sub-circuit comprises a first reset sub-circuit and a second reset sub-circuit,

the first reset sub-circuit is coupled to the first pull-up node, the low-level voltage terminal, and the first reset terminal, and configured to provide the signal of the low-level voltage terminal to the first pull-up node under control of the first reset terminal,

the second reset sub-circuit is coupled to the second reset terminal, the pull-up control node and the low-level voltage terminal, and configured to provide the signal of the low-level voltage terminal to the pull-up control node under control of the second reset terminal,

the second reset sub-circuit comprises a second transistor and a thirteenth transistor,

the second transistor has a control electrode coupled to the second reset terminal, a first electrode coupled to the pull-up control node, and a second electrode coupled to a second feedback node,

the thirteenth transistor has a control electrode coupled to the second reset terminal, a first electrode coupled to the second feedback node, and a second electrode coupled to the low-level voltage terminal,

the detection sub-shift register further comprises a second leakage prevention electronic circuit, and

the second leakage prevention sub-circuit is coupled to the pull-up control node, a high-level voltage terminal and the second feedback node, and configured to provide the signal of the high-level voltage terminal to the second feedback node under control of the pull-up control node, to maintain the on level of the pull-up control node.

14. The shift register of claim 13 , wherein the second leakage prevention sub-circuit comprises a fourteenth transistor,

the fourteenth transistor has a control electrode coupled to the pull-up control node, a first electrode coupled to the high-level voltage terminal, and a second electrode coupled to the second feedback node, and

the second feedback node is coupled to the second electrode of the first transistor.

15. The shift register of claim 5 , wherein the detection output sub-circuit comprises an eighth transistor and a ninth transistor,

the eighth transistor has a control electrode coupled to the first pull-up node, a first electrode coupled to the third clock signal terminal, and a second electrode coupled to the first output terminal,

the ninth transistor has a control electrode coupled to the first pull-up node, a first electrode coupled to the fourth clock signal terminal, and a second electrode coupled to the second output terminal,

the detection output control sub-circuit comprises a tenth transistor and an eleventh transistor,

the tenth transistor has a control electrode coupled to the first pull-down node, a first electrode coupled to the first output terminal, and a second electrode coupled to the low-level voltage terminal, and

the eleventh transistor has a control electrode coupled to the first pull-down node, a first electrode coupled to the second output terminal, and a second electrode coupled to the low-level voltage terminal, and

wherein the detection output sub-circuit further comprises a second capacitor and a third capacitor,

the second capacitor has a first end coupled to the first pull-up node, and a second end coupled to the first output terminal, and

the third capacitor has a first end coupled to the first pull-up node, and a second end coupled to the second output terminal.

16. The shift register of claim 3 , wherein the display sub-shift register comprises:

a display input sub-circuit coupled to a second input terminal, a fifth clock signal terminal, and a second pull-up node, and configured to provide a signal of the second input terminal to the second pull-up node under control of the fifth clock signal terminal;

a display output sub-circuit coupled to a sixth clock signal terminal, the second pull-up node, a cascade output terminal, and a third output terminal, and configured to provide a signal of the sixth clock signal terminal to the cascade output terminal and the third output terminal under control of the second pull-up node;

a display reset sub-circuit coupled to a third reset terminal, the second pull-up node and the low-level voltage terminal, and configured to provide the signal of the low-level voltage terminal to the second pull-up node under control of the third reset terminal;

a display output control sub-circuit coupled to the cascade output terminal, the third output terminal, a second pull-down node, and the low-level voltage terminal, and configured to provide the signal of the low-level voltage terminal to the cascade output terminal and the third output terminal under control of the second pull-down node;

a display node control sub-circuit coupled to a third control terminal, a fourth control terminal, the second pull-up node, the second pull-down node, and the low-level voltage terminal, and configured to provide the signal of the low-level voltage terminal to the second pull-down node under control of the third control terminal, the fourth control terminal, and the second pull-up node, and

the display control terminal is coupled to the cascade output terminal such that the detection sub-shift register does not operate when the display sub-shift register operates.

17. The shift register of claim 15 , wherein the display sub-shift register further comprises:

a second control sub-circuit coupled to the second pull-up node, a second pull-down node, a detection control terminal, a high-level voltage terminal, and the low-level voltage terminal, and configured to provide the signal of the low-level voltage terminal to the second pull-up node and the second pull-down node under control of the detection control terminal, and

the detection control terminal is coupled to the first pull-up node.

18. A gate driving circuit, comprising a plurality of shift registers cascaded in first to (N+1)-th stages, each of the shift registers being the shift register of claim 1 , and comprising a display sub-shift register and a detection sub-shift register,

wherein the display sub-shift register comprises a cascade output terminal, a second input terminal, a third output terminal, a third reset terminal, and a detection control terminal,

the first input terminal of the detection sub-shift register of the first stage of shift register is coupled to a first initial signal terminal, the first input terminal of the detection sub-shift register of the N-th stage of shift register is coupled to the first pull-up node of the detection sub-shift register of the (N−1)-th stage of shift register, and the second reset terminal of the detection sub-shift register of the N-th stage of shift register is coupled to the first pull-up node of the detection sub-shift register of the (N+1)-th stage of shift register,

the second input terminal of the display sub-shift register of the first stage of shift register is coupled to a second initial signal terminal, the second input terminal of the display sub-shift register of the N-th stage of shift register is coupled to the cascade output terminal of the display sub-shift register of the (N−1)-th stage of shift register, and the third reset terminal of the display sub-shift register of the N-th stage of shift register is coupled to the cascade output terminal of the display sub-shift register of the (N+1)-th stage of shift register,

the detection control terminal of the display sub-shift register of the N-th stage of shift register is coupled to the first pull-up node of the detection sub-shift register of the N-th stage of shift register, the cascade output terminal of the display sub-shift register of the N-th stage of shift register is coupled to a display control terminal of the detection sub-shift register of the N-th stage of shift register, and the third output terminal of the display sub-shift register of the N-th stage of shift register is coupled to the first output terminal of the detection sub-shift register of the N-th stage of shift register, and

N is an integer greater than or equal to two.

19. A display device, comprising the gate driving circuit of claim 18 .

20. A method of driving a shift register,

the shift register comprising a display sub-shift register and a detection sub-shift register coupled to the display sub-shift register,

the method comprising:

in a first stage, providing a signal of a second clock signal terminal having an on level to a first pull-up node of the detection sub-shift register, and providing a signal of a low-level voltage terminal to a first output terminal of the detection sub-shift register;

in a second stage, providing a signal of the second clock signal terminal having an off level to the first pull-up node of the detection sub-shift register, and providing the signal of the low-level voltage terminal to the first output terminal of the detection sub-shift register;

in a third stage, providing a signal of the second clock signal terminal having an on level to the first pull-up node of the detection sub-shift register, and providing a signal of a third clock signal terminal having an on level to the first output terminal of the detection sub-shift register;

in a fourth stage, providing the signal of the low-level voltage terminal to the first pull-up node and the first output terminal of the detection sub-shift register; and

in a fifth stage, making the first pull-up node of the detection sub-shift register remain a level in the fourth stage, and providing the signal of the low-level voltage terminal to the first output terminal of the detection sub-shift register,

wherein a time period in which the signal of the first pull-up node is at the on level at least partially overlaps with a time period in which the signal of the first output terminal is at the on level, and when the signal of the first pull-up node is at the off level, the signal of the first output terminal is at the off level.