Method of manufacturing semiconductor device
A method of manufacturing a semiconductor device from a semiconductor wafer in which a plurality of semiconductor chips are formed. The method includes a first process of forming an active region on a first main surface side of the semiconductor wafer and a second process of forming a first process control monitor (PCM) on a second main surface side of the semiconductor wafer. The method further includes before the second process, a third process of forming a second PCM on the first main surface side of the semiconductor wafer. The first PCM and the second PCM are formed at an area located at the same position in a plan view of the semiconductor wafer.
1. A method of manufacturing a semiconductor device from a semiconductor wafer in which a plurality of semiconductor chips are formed, the method comprising:
laying out a plurality of chip areas for the semiconductor chips in the semiconductor wafer, the semiconductor wafer having a first main surface and a second main surface opposite to the first main surface;
forming a plurality of active regions in the plurality of chip areas, respectively;
forming at the second main surface a first process control monitor (PCM) in a first area other than the chip areas in which the active regions are formed; and
concurrently performing an ion implantation by implanting ions at the first area to form the first PCM and at each of the chip areas of the second main surface of the semiconductor wafer respectively to form a corresponding one of the active regions.
2. The method according to claim 1 , further comprising
before forming the first PCM, forming at the first main surface of the semiconductor wafer a second PCM in a second area other than the chip areas in which the active regions are formed, wherein
the first area and the second area entirely overlap each other in a plan view of the semiconductor wafer.
3. The method according to claim 1 , wherein
forming a plurality of active regions includes performing a plurality of ion implantations in the plurality of active regions at the second main surface, and
only one of the plurality of ion implantations performed in the active regions at the second main surface is concurrently performed at the first area to form the evaluation portion.
4. The method according to claim 1 , wherein
forming the plurality of active regions includes performing a plurality of ion implantations in the plurality of active regions at the second main surface, and
a combination of more than one ion implantation among the plurality of ion implantations performed in the active regions at the second main surface is concurrently performed at the first area to form the evaluation portion.
5. The method according to claim 1 , wherein forming the first PCM includes forming a marker at the first area for identifying a position of the first PCM relative to an entire area of the second main surface of the semiconductor wafer.
6. The method according to claim 1 , wherein
the first PCM includes a plurality of marker portions, and
forming the first PCM includes forming a first marker portion disposed, as viewed in a plan view of the semiconductor wafer, at a center position of the second main surface of the semiconductor wafer, and a second marker portion disposed, as viewed in a plan view of the semiconductor wafer, at a peripheral position of the second main surface of the semiconductor wafer.
7. The method according to claim 1 , wherein
forming a plurality of active regions includes forming a first load electrode on the first main surface, and a second load electrode on the second main surface so that a current passes between the first load electrode and the second load electrode.
8. The method according to claim 7 , wherein
forming a plurality of active regions includes forming at the first main surface a control electrode that controls the current passing between the first load electrode and the second load electrode.
9. A method of manufacturing a semiconductor device from a semiconductor wafer in which a plurality of semiconductor chips are formed, the method comprising:
laying out a plurality of chip areas for the semiconductor chips in the semiconductor wafer, the semiconductor wafer having a first main surface and a second main surface opposite to the first main surface;
performing at the first main surface of the semiconductor wafer, a plurality of forming steps for forming a plurality of first active regions in the chip areas;
forming at the first main surface of the semiconductor wafer, a process control monitor (PCM) in a second area other than the chip areas in which the first active regions are to be formed;
performing at the second main surface of the semiconductor wafer, a plurality of forming steps for forming a plurality of second active regions in the chip areas;
forming at the second main surface an other PCM in a first area other than the chip areas in which the second active regions are formed; and
concurrently performing an ion implantation by implanting ions at the first area to form the first PCM and at each of the chip areas of the second main surface of the semiconductor wafer respectively to form a corresponding one of the active regions.
10. A method of manufacturing a semiconductor device from a semiconductor wafer in which a plurality of semiconductor chips are formed, the method comprising:
laying out a plurality of chip areas for the semiconductor chips in the semiconductor wafer, the semiconductor wafer having a first main surface and a second main surface opposite to the first main surface;
forming a plurality of active regions respectively in corresponding ones of the plurality of chip areas; and
forming at the second main surface a first process control monitor (PCM) in a first area other than the chip areas in which the active regions are formed, wherein
the first PCM includes a plurality of marker portions, and
forming the first PCM includes forming a first marker portion disposed, as viewed in a plan view of the semiconductor wafer, at a center position of the second main surface of the semiconductor wafer, and a second marker portion disposed, as viewed in a plan view of the semiconductor wafer, at a peripheral position of the second main surface of the semiconductor wafer.