Multi-mode stacked amplifier
Aspects of this disclosure relate to an amplification circuit that includes a stacked amplifier and a bias circuit. The stacked amplifier includes at least a first transistor and a second transistor in series with each other. The stacked amplifier is operable in at least a first mode and a second mode. The bias circuit is configured to bias the second transistor to a linear region of operation in the first mode and to bias the second transistor as a switch in the second mode. In certain embodiments, the amplification circuit can be a power amplifier stage configured to receive a supply voltage that has a different voltage level in the first mode than in the second mode.
1. A multi-mode amplifier system comprising:
a first amplifier stage having an output;
a second amplifier stage having an input electrically coupled to the output of the first amplifier stage by way of a matching network, the second amplifier stage including a first transistor and a second transistor in series with each other, the second amplifier stage operable in a first mode and a second mode;
a supply control circuit configured to provide a supply voltage to the second amplifier stage such that the supply voltage has a different voltage level in the first mode than in the second mode; and
a bias circuit configured to bias the second transistor to operate in a linear region of operation in the first mode, and the bias circuit configured to bias the second transistor as a switch in the second mode.
2. The multi-mode amplifier system of claim 1 wherein the second amplifier stage includes a third transistor in series with the second transistor.
3. The multi-mode amplifier system of claim 2 wherein the first amplifier stage includes two transistors in series with each other, and the second amplifier stage includes more transistors in series with each other than the first amplifier stage.
4. The multi-mode amplifier system of claim 1 wherein the first amplifier stage includes two transistors in series with each other.
5. The multi-mode amplifier system of claim 1 wherein the first transistor and the second transistor are semiconductor-on-insulator transistors.
6. The multi-mode amplifier system of claim 1 further comprising a class F output matching network electrically connected to an output of the second amplifier stage.
7. The multi-mode amplifier system of claim 1 further comprising a class AB output matching network electrically connected to an output of the second amplifier stage.
8. A multi-mode amplifier system comprising:
a first amplifier stage having an output;
a second amplifier stage having an input electrically coupled to the output of the first amplifier stage by way of a matching network, the second amplifier stage including a first transistor and a second transistor in series with each other, the second amplifier stage operable in a first mode and a second mode, the multi-mode amplifier system being arranged to provide a first supply voltage to the first amplifier stage and a second supply voltage to the second amplifier stage, the second supply voltage having a higher voltage level than the first supply voltage in the first mode; and
a bias circuit configured to bias the second transistor to operate in a linear region of operation in the first mode, and the bias circuit configured to bias the second transistor as a switch in the second mode.
9. The multi-mode amplifier system of claim 8 wherein the first amplifier stage includes two transistors in series with each other.
10. A multi-mode amplifier system comprising:
a first amplifier stage having an output;
a second amplifier stage having an input electrically coupled to the output of the first amplifier stage by way of a matching network, the second amplifier stage including a first transistor and a second transistor in series with each other, the second amplifier stage operable in a first mode and a second mode, the multi-mode amplifier system being arranged to provide a first supply voltage to the first amplifier stage and a second supply voltage to the second amplifier stage, the second supply voltage having a lower voltage level than the first supply voltage in the second mode; and
a bias circuit configured to bias the second transistor to operate in a linear region of operation in the first mode, and the bias circuit configured to bias the second transistor as a switch in the second mode.
11. The multi-mode amplifier system of claim 10 wherein the second supply voltage has a higher voltage level than the first supply voltage in the first mode.
12. A method of amplifying a radio frequency signal in multiple modes of operation, the method comprising:
amplifying a radio frequency signal received from an input amplifier stage with a stacked amplifier stage in a first mode, the stacked amplifier stage including a transistor biased in a linear mode of operation in the first mode;
biasing the transistor of the stacked amplifier stage to operate in a saturation region for a second mode, a supply voltage for the stacked power amplifier stage having a lower voltage level in the second mode than in the first mode; and
amplifying the radio frequency signal with the stacked amplifier stage in the second mode, the transistor of the stacked power amplifier stage being biased in the saturation region of operation in the second mode.
13. The method of claim 12 further comprising providing an input stage supply voltage to the input amplifier stage such that the supply voltage has a substantially constant voltage level in the first mode and the second mode.
14. The method of claim 13 wherein the substantially constant voltage level of the input stage supply voltage is higher than the voltage level of the supply voltage in the second mode.
15. The method of claim 12 wherein the input amplifier stage includes a stacked amplifier with fewer transistors arranged in series with each other in a stack than the stacked power amplifier stage.
16. The method of claim 12 wherein the transistor is a silicon-on-insulator transistor.
17. A front end system comprising:
a power amplifier circuit including a first amplifier stage having an output; a second amplifier stage having an input electrically coupled to an output of the first amplifier stage by way of a matching network, the second amplifier stage including a first transistor and a second transistor in series with each other, the second amplifier stage operable in a first mode and a second mode; and a bias circuit configured to bias the second transistor to operate in a linear region of operation in the first mode, and the bias circuit configured to bias the second transistor as a switch in the second mode; and
a multi-throw switch including a first throw electrically coupled to the power amplifier circuit.
18. The front end system of claim 17 wherein further comprising a low noise amplifier, the multi-throw switch including a second throw electrically coupled to the low noise amplifier.
19. The front end system of claim 18 wherein the power amplifier circuit and the low noise amplifier are on a single silicon-on-insulator die.
20. The front end system of claim 17 further comprising a bypass path electrically coupled to a second throw of the multi-throw switch.