IP Library Granted Patent US 11,083,090
Granted Patent B2
US 11,083,090 · App. 16/511,651 · Granted Aug 3, 2021

Multi-layer ceramic electronic component, method of producing a multi-layer ceramic electronic component, and substrate with a built-in electronic component

Inventor: Takashi Sasaki (Tokyo, JP)
Assignee: Taiyo Yuden Co., Ltd.
H05K1/186H01G4/224H01G4/232H01G4/248H05K1/182H05K1/183H05K1/185H05K2201/09154H05K2201/09827H05K2201/09854H05K2201/10015H05K2201/10636
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Quick Facts
Patent No.
US 11,083,090
App. No.
16/511,651
Granted
Aug 3, 2021
Kind
B2
Abstract

A multi-layer ceramic electronic component includes: a ceramic body including internal electrodes laminated in one axial direction and having a main surface facing in the one axial direction; and an external electrode including a base layer including a step portion formed on the main surface, and a plated layer formed on the base layer, the external electrode being connected to the internal electrodes.

Claims (18)

1. A substrate with a built-in electronic component comprising:

a multi-layer ceramic electronic component including

a ceramic body including internal electrodes laminated in a first axial direction and having a main surface facing in the first axial direction, and

an external electrode including

a base layer including a step portion formed on the main surface, and

a plated layer formed on the base layer, the external electrode being connected to the internal electrodes;

a housing layer housing the multi-layer ceramic electronic component; and

a wiring layer including

an insulating layer formed on the housing layer,

a conductor layer formed on the insulating layer, and

a via configured for interlayer connection and connected to the external electrode and the conductor layer and formed in the insulating layer to face the step portion in the first axial direction,

wherein the plated layer includes a difference in level resulting from the shape of the step portion,

wherein the via penetrates the insulating layer from the conductor layer to the external electrode and is filled with a conductor,

wherein the conductor has a connection surface in contact with the external electrode,

wherein the via is disposed to face the difference in level of the plated layer, and

wherein the connection surface has an irregular shape corresponding to the difference in level of the plated layer,

wherein the plated layer comprises, on the main surface, an upper stage surface, a lower stage surface, and a standing surface that connects the upper stage surface and the lower stage surface, and

wherein the connection surface is in direct contact with the lower stage surface, the standing surface, and only a portion of the upper stage surface.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 27, 2019
From: SASAKI, TAKASHI
To: TAIYO YUDEN CO., LTD.
Reel/Frame 051126/0181 →
Priority Claims (1)
JP JP2018-137508 · Jul 23, 2018 · national
Continuity (1)
Related Publication 20200029438A1 · Jan 23, 2020