Misprediction of predicted taken branches in a data processing apparatus
Apparatus and a method of operating the same is disclosed. Instruction fetch circuitry is provided to fetch a block of instructions from memory and branch prediction circuitry to generate branch prediction indications for each branch instruction present in the block of instructions. The branch prediction circuitry is responsive to identification of a first conditional branch instruction in the block of instructions that is predicted to be taken to modify a branch prediction indication generated for the first conditional branch instruction to include a subsequent branch status indicator. When there is a subsequent branch instruction after the first conditional branch instruction in the block of instructions that is predicted to be taken the subsequent branch status indicator has a first value, and otherwise the subsequent branch status indicator has a second value. This supports improved handling of a misprediction as taken.
1. Apparatus comprising:
instruction fetch circuitry to fetch a block of instructions from memory; and
branch prediction circuitry to generate branch prediction indications for each branch instruction present in the block of instructions,
wherein the branch prediction circuitry is responsive to identification of a first conditional branch instruction in the block of instructions that is predicted to be taken to modify a branch prediction indication generated for the first conditional branch instruction to include a status indicator for subsequent branch instructions in the block of instructions,
wherein when there is a subsequent branch instruction after the first conditional branch instruction in the block of instructions and the subsequent branch instruction is predicted to be taken the status indicator has a first value, and otherwise the status indicator has a second value.
2. The apparatus as claimed in claim 1 , further comprising branch resolution circuitry to determine a resolution status for branch instructions,
and the branch prediction circuitry is responsive to a not-taken resolution status determined by the branch resolution circuitry for the first conditional branch instruction in the block of instructions to proceed with generating branch prediction indications:
from a first instruction of a next block of instructions which subsequently follows the block of instructions, when the status indicator has the second value; and
from a first instruction of a target block of instructions to which the subsequent branch instruction leads, when the status indicator has the first value.
3. The apparatus as claimed in claim 1 , wherein the status indicator is a 1-bit value.
4. The apparatus as claimed in claim 1 , further comprising branch target storage, wherein the branch prediction circuitry is further responsive to the identification of the first conditional branch instruction in the block of instructions that is predicted to be taken, when there is the subsequent branch instruction after the first conditional branch instruction in the block of instructions that is predicted to be taken, to cause a target address of the subsequent branch instruction to be stored in the branch target storage.
5. The apparatus as claimed in claim 4 , wherein the branch prediction circuitry comprises branch prediction confidence circuitry to generate a prediction confidence indication in association with each branch prediction indication which it generates,
and wherein storage of the target address of the subsequent branch instruction in the branch target storage is dependent on a value of the prediction confidence indication.
6. The apparatus as claimed in claim 5 , wherein the branch prediction circuitry is responsive to the value of the prediction confidence indication not being above a predetermined threshold value to cause the target address of the subsequent branch instruction to be stored in the branch target storage.
7. The apparatus as claimed in claim 5 , wherein the branch prediction circuitry is responsive to the value of the prediction confidence indication being above a predetermined threshold value to prevent the target address of the subsequent branch instruction from being stored in the branch target storage.
8. The apparatus as claimed in 6 , wherein the branch prediction confidence circuitry is responsive to an unconditional branch to generate the prediction confidence indication in association with the unconditional branch with a value above the predetermined threshold value.
9. The apparatus as claimed in claim 4 , wherein storage of the target address of the subsequent branch instruction in the branch target storage is dependent on a relative priority of an agent executing the block of instructions.
10. The apparatus as claimed in claim 9 , wherein the agent executing the block of instructions is a thread within a multi-threaded execution environment.
11. The apparatus as claimed in claim 9 , wherein the branch prediction circuitry comprises branch prediction confidence circuitry to generate a prediction confidence indication in association with each branch prediction indication which it generates, and the branch prediction circuitry is responsive to the relative priority of an agent executing the block of instructions when generating the value of the prediction confidence indication, and the branch prediction circuitry is responsive to the value of the prediction confidence indication being below a predetermined threshold value to cause the target address of the subsequent branch instruction to be stored in the branch target storage.
12. The apparatus as claimed in claim 1 , wherein the instruction fetch circuitry is arranged to fetch a pair of blocks comprising the block of instructions from memory,
and the branch prediction circuitry is arranged to generate branch prediction indications for each branch instruction present in the pair of blocks of instructions.
13. The apparatus as claimed in claim 1 , wherein the branch prediction circuitry is arranged to generate branch prediction indications for each branch instruction present in the block of instructions in a single processing cycle.
14. The apparatus as claimed in claim 1 , wherein the block of instructions is aligned to a predefined multiple-byte boundary in memory.
15. The apparatus as claimed in claim 14 , wherein the block of instructions is 32-byte aligned.
16. A method of branch prediction in a data processing apparatus comprising:
fetching a block of instructions from memory;
generating branch prediction indications for each branch instruction present in the block of instructions;
identifying a first conditional branch instruction in the block of instructions that is predicted to be taken; and
modifying a branch prediction indication generated for the first conditional branch instruction to include a status indicator for subsequent branch instructions in the block of instructions,
wherein when there is a subsequent branch instruction after the first conditional branch instruction in the block of instructions and the subsequent branch instruction is predicted to be taken the status indicator has a first value, and otherwise the status indicator has a second value.
17. Apparatus comprising:
means for fetching a block of instructions from memory;
means for generating branch prediction indications for each branch instruction present in the block of instructions;
means for identifying a first conditional branch instruction in the block of instructions that is predicted to be taken; and
means for modifying a branch prediction indication generated for the first conditional branch instruction to include a status indicator for subsequent branch instructions in the block of instructions,
wherein when there is a subsequent branch instruction after the first conditional branch instruction in the block of instructions and the subsequent branch is predicted to be taken the status indicator has a first value, and otherwise the status indicator has a second value.