Memory system, memory controller and operating method thereof
A memory system, a memory controller and an operating method thereof, capable of reducing the storage capacity of data in relation with map tables, by, in the case where N map entries respectively corresponding to N consecutive physical address regions exist among map entries included in a first map table in a memory device, adding a group map entry indicating a mapping information corresponding to the group of the N number of consecutive physical address regions, to a second map table included in the memory device.
1. A memory system comprising:
a memory device configured to store a plurality of map tables, each including a plurality of map entries, each indicating mapping information between one or more logical addresses and one or more physical addresses; and
a memory controller configured to control the memory device,
wherein the plurality of map tables include a first map table and a second map table,
wherein a size of a physical address region corresponding to each of a plurality of map entries in the second map table is N times a size of a physical address region corresponding to each of a plurality of map entries in the first map table, where N is a natural number of 2 or greater, and
wherein, in a case where N map entries respectively corresponding to N consecutive physical address regions exist among the plurality of map entries in the first map table, the memory controller adds a group map entry indicating mapping information corresponding to a group of the N consecutive physical address regions to the second map table.
2. The memory system according to claim 1 , wherein the memory controller erases the N map entries from the first map table when the group map entry is added to the second map table.
3. The memory system according to claim 1 , wherein the memory controller is further configured to:
update the plurality of map entries in the first map table, by a unit of a first map write segment; and
update the plurality of map entries in the second map table, by a unit of a second map write segment different from the first map write segment.
4. The memory system according to claim 1 , wherein the memory controller is further configured to:
load a map cache entry including at least some of the plurality of map entries included in any one map table among the plurality of map tables, to a map cache,
load at least some of the plurality of map entries included in the first map table, to the map cache, by a unit of a first map read segment, and
load at least some of the plurality of map entries included in the second map table, to the map cache, by a unit of a second map read segment different from the first map read segment.
5. The memory system according to claim 4 , wherein the memory controller is further configured to identify mapping information of a target physical address corresponding to a target logical address in the map cache by
determining a target map table corresponding to the target logical address among the plurality of map tables, based on target map table indicating information indicating a map table corresponding to the target logical address, and
searching for the mapping information of the target physical address in map cache entries including some map entries of the target map table, among map cache entries in the map cache.
6. The memory system according to claim 5 , wherein the target map table indicating information is stored as a bitmap corresponding to the target logical address.
7. The memory system according to claim 5 , wherein the memory controller is further configured to determine the target physical address corresponding to the target logical address, based on an offset between the target logical address and a start logical address in the mapping information corresponding to the target logical address.
8. The memory system according to claim 1 , wherein
each of the plurality of map tables comprises a first layer table including a plurality of first layer table entries and one or more second layer tables, and
each of the one or more second layer tables includes some of the plurality of map entries, and corresponds to one of the plurality of first layer table entries.
9. The memory system according to claim 8 , wherein the memory controller caches all first layer table entries in the first layer table, in a first layer cache, for each of the plurality of map tables.
10. The memory system according to claim 8 , wherein the memory controller is further configured to when mapping information of a target physical address corresponding to a target logical address is included in the first map table and a first layer table entry corresponding to a second layer table including the mapping information is not cached in the first layer cache,
search for the mapping information in map cache entries including some of the map entries of the first map table and map cache entries including some of the map entries of the second map table, among the map cache entries in the map cache.
11. The memory system according to claim 10 , wherein, the memory controller searches the map cache entries including some of the map entries of the first map table with a higher priority than the map cache entries including some of the map entries of the second map table, among the map cache entries in the map cache.
12. A memory controller comprising:
a memory interface configured to communicate with a memory device which stores a plurality of map tables, each including a plurality of map entries, each indicating mapping information between one or more logical addresses and one or more physical addresses; and
a control circuit configured to control the memory device,
wherein the plurality of map tables include a first map table and a second map table,
wherein a size of a physical address region corresponding to each of a plurality of map entries in the second map table is N times a size of a physical address region corresponding to each of a plurality of map entries in the first map table, where N is a natural number of 2 or greater, and
wherein, in a case where N map entries corresponding to N consecutive physical address regions exist among the plurality of map entries in the first map table, the control circuit adds a group map entry indicating mapping information corresponding to a group of the N consecutive physical address regions to the second map table.
13. The memory controller according to claim 12 , wherein the control circuit erases the N map entries from the first map table when the group map entry is added to the second map table.
14. The memory controller according to claim 12 , wherein the control circuit is further configured to:
update the plurality of map entries included in the first map table, by a unit of a first map write segment; and
update the plurality of map entries included in the second map table, by a unit of a second map write segment different from the first map write segment.
15. The memory controller according to claim 12 , wherein
the control circuit comprises a working memory which stores a map cache which caches some of the map entries included in any one among the plurality of map tables, and
the control circuit is further configured to:
load at least some of the plurality of map entries included in any one map table among the plurality of map tables to the map cache; and
identify mapping information of a target physical address corresponding to a target logical address in the map cache by:
determining a target map table corresponding to the target logical address among the plurality of map tables, based on a target map table indicating information indicating a map table corresponding to the target logical address, and
searching for the mapping information of the target physical address in map cache entries including some map entries of the target map table, among map cache entries of the map cache.
16. The memory controller according to claim 15 , wherein the control circuit is further configured to determine the target physical address corresponding to the target logical address, based on an offset between the target logical address and a start logical address in the mapping information corresponding to the target logical address.
17. The memory controller according to claim 12 , wherein
each of the plurality of map tables comprises a first layer table including a plurality of first layer table entries and one or more second layer tables, and
each of the one or more second layer tables includes a part of the plurality of map entries, and corresponds to any one of the plurality of first layer table entries.
18. The memory controller according to claim 17 , wherein the control circuit caches all first layer table entries included in the first layer table, in a first layer cache, for each of the plurality of map tables.
19. The memory controller according to claim 17 , wherein the control circuit is further configured to, when mapping information of a target physical address corresponding to a target logical address is included in the first map table and a first layer table entry corresponding to a second layer table including the mapping information is not cached in the first layer cache,
search for the mapping information in map cache entries including some of the map entries of the first map table and map cache entries including some of the map entries of the second map table, among the map cache entries in the map cache.