IP Library › Granted Patent US 11,088,041
Granted Patent B2
US 11,088,041 · App. 16/572,612 · Granted Aug 10, 2021

Semiconductor packages with shortened talking path

Inventors: Hsien-Wei Chen (Hsinchu, TW); Jie Chen (New Taipei, TW); Ming-Fa Chen (Taichung, TW); Chih-Chia Hu (Taipei, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L23/10H01L23/3142H01L23/5226H01L23/5384H01L23/5385H01L23/5386H01L25/0657H01L2224/04105
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Quick Facts
Patent No.
US 11,088,041
App. No.
16/572,612
Granted
Aug 10, 2021
Kind
B2
Abstract

Semiconductor packages are disclosed. A semiconductor package includes an integrated circuit, a first die and a second die. The first die includes a first bonding structure and a first seal ring. The first bonding structure is bonded to the integrated circuit and disposed at a first side of the first die. The second die includes a second bonding structure. The second bonding structure is bonded to the integrated circuit and disposed at a first side of the second die. The first side of the first die faces the first side of the second die. A first portion of the first seal ring is disposed between the first side and the first bonding structure, and a width of the first portion is smaller than a width of a second portion of the first seal ring.

Claims (29)

1. A semiconductor package, comprising:

an integrated circuit;

a first die comprising a first bonding structure and a first seal ring, the first bonding structure bonded to the integrated circuit and disposed at a first side of the first die; and

a second die comprising a second bonding structure, the second bonding structure bonded to the integrated circuit and disposed at a first side of the second die, the first side of the first die facing the first side of the second die, wherein a first portion of the first seal ring is disposed between the first side and the first bonding structure, and a width of the first portion is smaller than a width of a second portion of the first seal ring.

2. The semiconductor package of claim 1 , wherein the integrated circuit comprises a plurality of third bonding structures and a conductive feature, and the conductive feature is disposed between and electrically connected to the third bonding structure bonded to the first bonding structure and the third bonding structure bonded to the second bonding structure.

3. The semiconductor package of claim 2 , wherein the portion of the first seal ring is overlapped with the conductive feature from a top view.

4. The semiconductor package of claim 2 , wherein the conductive feature is extended in a direction perpendicular to the first side of the first die.

5. The semiconductor package of claim 1 , wherein the second portion of the first seal ring is disposed at a second side connecting to the first side, a third side connecting to the first side and a fourth side opposite to the first side of the first die.

6. The semiconductor package of claim 1 , wherein the first die further comprises an additional bonding structure at a second side of the first die, and the shortest distance between the first bonding structure and the first side of the first die is smaller than the shortest distance between the additional bonding structure and the second side of the first die.

7. The semiconductor package of claim 1 , wherein the second die further comprises a second seal ring, and a first portion of the second seal ring between the first side of the second die and the second bonding structure has a width smaller than a second portion of the second seal ring.

8. The semiconductor package of claim 1 , further comprising an encapsulant disposed between the first side of the first die and the first side of the second die.

9. A semiconductor package, comprising:

an integrated circuit, comprising a conductive feature;

a first die comprising a first bonding structure and a first seal ring, the first bonding structure bonded to the integrated circuit and disposed at a first side of the first die; and

a second die comprising a second bonding structure, the second bonding structure bonded to the integrated circuit and disposed at a first side of the second die, the first side of the first die facing the first side of the second die, wherein the conductive feature is disposed between and electrically connected to the first bonding structure and the second bonding structure, and the first seal ring is not overlapped with the conductive feature from a top view.

10. The semiconductor package of claim 9 , wherein the first seal ring is disposed at a second side connecting to the first side, a third side connecting to the first side and a fourth side opposite to the first side of the first die.

11. The semiconductor package of claim 9 , wherein the conductive feature is extended in a direction perpendicular to the first side of the first die.

12. The semiconductor package of claim 9 , wherein the second die further comprises a second seal ring, and the second seal ring is not overlapped with the conductive feature from a top view.

13. The semiconductor package of claim 9 , wherein the first die further comprises an additional bonding structure at a second side of the first die, and the shortest distance between the first bonding structure and the first side of the first die is smaller than the shortest distance between the additional bonding structure and the second side of the first die.

14. A semiconductor package, comprising:

an integrated circuit comprising a first bonding structure, a second bonding structure and a conductive bridge connecting and being in direct contact with the first bonding structure and the second bonding structure;

a first die, comprising a third bonding structure and a seal ring, wherein the third bonding structure is disposed at a first side of the first die and bonded to the first bonding structure, and the seal ring is disposed at a second side different from the first side of the first die; and

a second die, comprising a fourth bonding structure bonded to the second bonding structure, wherein there is no seal ring overlapped with the conductive bridge from a top view.

15. The semiconductor package of claim 14 , wherein the second die is a seal ring-free die.

16. The semiconductor package of claim 14 , further comprising an encapsulant encapsulating the first die and the second die, wherein a sidewall of the encapsulant is substantially flush with a sidewall of the integrate circuit.

17. The semiconductor package of claim 14 , wherein the conductive bridge is continuously extended between the first bonding structure and the second bonding structure.

18. The semiconductor package of claim 14 , wherein the integrated circuit further comprises a first bonding dielectric layer encapsulating the first bonding structure and the second bonding structure, and the first die further comprises a second bonding dielectric layer encapsulating the third bonding structure and bonded to the first bonding dielectric layer.

19. The semiconductor package of claim 14 , wherein the first die further comprises a conductive feature disposed at the first side of the first die and being in direct contact with the third bonding structure, the third bonding structure is disposed between the integrated circuit and the conductive feature, and from the top view, there is no seal ring disposed between the conductive feature and the first side of the first die.

20. The semiconductor package of claim 14 , wherein the seal ring is further disposed at a third side and a fourth side different from the first side and the second side.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 23, 2019
From: CHEN, HSIEN-WEI; CHEN, JIE; CHEN, MING-FA; HU, CHIH-CHIA
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 050796/0508 →
Continuity (1)
Related Publication 20210082779A1 · Mar 18, 2021
Cited By (2)
US 12,417,952 US 12,512,429