IP Library › Granted Patent US 11,088,204
Granted Patent B2
US 11,088,204 · App. 16/642,865 · Granted Aug 10, 2021

Three terminal selectors for memory applications and their methods of fabrication

Inventors: Ravi Pillarisetty (Portland, OR); Abhishek A. Sharma (Hillsboro, OR); Van H. Le (Portland, OR); Jack T. Kavalieros (Portland, OR); Willy Rachmady (Beaverton, OR)
Assignee: Intel Corporation
H01L27/2436G11C11/161G11C11/1659G11C13/003H01L27/228H01L43/02H01L43/12H01L45/16G11C2213/15G11C2213/74G11C2213/79
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Quick Facts
Patent No.
US 11,088,204
App. No.
16/642,865
Granted
Aug 10, 2021
Kind
B2
Abstract

A memory device includes a first electrode, a non-volatile memory element having a first terminal and a second terminal, where the first terminal is coupled to the first electrode. The memory device further includes a selector having a first terminal, a second terminal and a sidewall between the first and second terminals, where the second terminal of the selector is coupled to the first terminal of the non-volatile memory element. A second electrode is coupled to the second terminal of the selector and a third electrode laterally adjacent to the sidewall of the selector.

Claims (41)

1. A memory device comprising:

a first electrode;

a non-volatile memory element having a first terminal and a second terminal, wherein the first terminal is coupled to the first electrode;

a selector having a first terminal coupled to a second terminal through an insulator layer therebetween, wherein the first terminal of the selector is further coupled to the second terminal of the non-volatile memory element;

a second electrode coupled to the second terminal of the selector; and

a third electrode laterally adjacent to a sidewall of the insulator layer.

2. The memory device of claim 1 , wherein the selector comprises a metal-insulator-metal stack.

3. The memory device of claim 1 , wherein the insulator layer comprises oxygen and at least one of hafnium, tantalum, niobium and vanadium.

4. The memory device of claim 1 , wherein the insulator layer comprises a phase change material.

5. The memory device of claim 4 , wherein the phase change material comprises at least Ge and Te.

6. The memory device of claim 1 , wherein the insulator layer comprises a filament extending through at least a partial thickness of the insulator layer.

7. The memory device of claim 1 , wherein the insulator layer has a thickness between 1 nm and 50 nm.

8. The memory device of claim 2 , wherein the third electrode is laterally adjacent to a sidewall of the metal-insulator-metal stack.

9. The memory device of claim 1 , further comprising a dielectric layer between the third electrode and the sidewall of the insulator layer.

10. The memory device of claim 9 , wherein the dielectric layer comprises oxygen and one or more metals.

11. The memory device of claim 1 , wherein the non-volatile memory element comprises a magnetic tunnel junction (MTJ) device, the MTJ device comprising:

a fixed magnet;

a tunnel barrier above the fixed magnet; and

a free magnet above the tunnel barrier.

12. The memory device of claim 1 , wherein the non-volatile memory element comprises a resistive RAM device.

13. The memory device of claim 1 , wherein:

the selector comprises a first selector and the memory device further comprises a second selector and a third selector;

the first electrode and the second electrode are coupled to the first selector and to the second selector; and

the third electrode, extends in a direction orthogonal to the first and second electrodes and is coupled to the first selector and to the third selector.

14. A method to fabricate a memory device, comprising:

forming a first electrode;

forming a non-volatile memory element coupled to the first electrode;

forming a selector comprising a metal-insulator-metal (MIM) stack coupled to the non-volatile memory element;

depositing a second electrode adjacent to a sidewall of the selector; and

forming a third electrode coupled to the selector.

15. The method of claim 14 , wherein depositing the second electrode comprises depositing a conductive material laterally adjacent to a dielectric layer that is laterally adjacent to a sidewall of the MIM stack.

16. The method of claim 14 , wherein forming the selector further comprises depositing the MIM stack, and forming the sidewall of the selector by patterning the MIM stack.

17. The method of claim 14 , wherein forming the third electrode further comprises:

depositing a dielectric layer over the selector and the second electrode; and

landing a conductive via on a metal layer of the MIM stack.

18. The method of claim 14 , wherein forming the non-volatile memory element further comprises forming an MTJ memory device.

19. A method of operating a memory device, the method comprising:

applying a first voltage to a first terminal of a selector having a second terminal coupled to a non-volatile memory device, wherein the selector comprises a metal-insulator-metal (MIM) stack;

setting a threshold voltage of the selector by applying a second voltage to a third terminal of the selector;

sensing a state of the memory device by measuring a charge flow through the memory device.

20. The method of claim 19 , wherein the first voltage is between 0 and 50 mV, the second voltage is between 2V and 3V, and the threshold voltage is less than 50 my.

Continuity (1)
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