Integrated circuit and electrostatic discharge protection circuit thereof
An electrostatic discharge protection circuit is provided. The electrostatic discharge protection circuit includes an electrostatic discharge detection circuit, a discharge circuit, and a switch. The electrostatic discharge detection circuit detects whether an electrostatic discharge event occurs at the bounding pad to generate a first detection circuit. The discharge circuit receives the first detection signal. When the electrostatic discharge event occurs at the bounding pad, the discharge circuit provides a discharge path between the bounding pad and a ground terminal according to the first detection signal. The switch is coupled between the core circuit and the ground terminal and controlled by the first detection signal. When the electrostatic discharge event occurs at the bounding pad, the switch is turned off according to the first detection signal.
1. An electrostatic discharge protection circuit coupled to a bounding pad and a core circuit, comprising:
an electrostatic discharge detection circuit detecting whether an electrostatic discharge event occurs at the bounding pad to generate a first detection signal;
a discharge circuit receiving the first detection signal, wherein when the electrostatic discharge event occurs at the bounding pad, the discharge circuit provides a discharge path between the bounding pad and a ground terminal according to the first detection signal;
a switch coupled between the core circuit and the ground terminal and controlled by the first detection signal, wherein when the electrostatic discharge event occurs at the bounding pad, the switch is turned off according to the first detection signal; and
a first P-type transistor having a first terminal coupled to the bounding pad, a second terminal coupled to the core circuit, and a control terminal,
wherein when the core circuit does not operate in a normal operation mode, the control terminal of the first P-type transistor is in a floating state.
2. The electrostatic discharge protection circuit as claimed in claim 1 , wherein the core circuit operates in the normal operation mode, the control terminal of the first P-type transistor receives a control signal.
3. The electrostatic discharge protection circuit as claimed in claim 1 , wherein the switch comprises:
an N-type transistor having a first terminal coupled to the core circuit, a second terminal coupled to the ground terminal, and a control terminal receiving the first detection signal.
4. The electrostatic discharge protection circuit as claimed in claim 1 further comprising:
a buffer, coupled between the electrostatic discharge detection circuit and the switch, receiving the first detection signal, generating a buffering signal according to the first detection signal, and providing the buffering signal to the switch,
wherein when the electrostatic discharge event occurs at the bounding pad, the switch is turned off according to the buffering signal.
5. The electrostatic discharge protection circuit as claimed in claim 4 , wherein the buffer circuit comprises:
a second P-type transistor having a first terminal coupled to the bounding terminal, a second terminal coupled to a first node, and a control terminal receiving the first detection signal;
a first N-type transistor having a first terminal coupled to the first node, a second terminal coupled to the ground terminal, and a control terminal receiving the first detection signal;
a third P-type transistor having a first terminal coupled to the bounding terminal, a second terminal coupled to a second node, and a control terminal coupled to the first node; and
a second N-type transistor having a first terminal coupled to the second node, a second terminal coupled to the ground terminal, and a control terminal coupled to the first node;
wherein the buffering signal is generated at the second node.
6. The electrostatic discharge protection circuit as claimed in claim 1 , wherein the discharge circuit generates a second detection signal which is inverse to the first detection signal, and the electrostatic discharge protection circuit further comprises:
an inverter, coupled between the discharge circuit and the switch, receiving the second detection signal, generating an inverted signal according to the second detection signal, and providing the inverted signal to the switch,
wherein when the electrostatic discharge event occurs at the bounding pad, the switch is turned off according to the inverted signal.
7. The electrostatic discharge protection circuit as claimed in claim 1 , further comprising:
an inverter, coupled between the electrostatic discharge detection circuit and the switch, receiving the first detection signal, generating an inverted signal according to the first detection signal, and providing the inverted signal to the switch,
wherein when the electrostatic discharge event occurs at the bounding pad, the switch is turned off according to the inverted signal.
8. The electrostatic discharge protection circuit as claimed in claim 7 , wherein the electrostatic discharge detection circuit comprises:
a capacitor coupled between the bounding pad and a first node; and
a resistor coupled between the first node and the ground terminal,
wherein the first detection signal is generated at the first node.
9. An integrated circuit comprising:
a core circuit, coupled to a bounding pad, having a power terminal coupled to a ground terminal; and
an electrostatic discharge protection circuit coupled to the bounding pad and the core circuit, wherein when an electrostatic discharge event occurs at the bounding pad, the electrostatic discharge protection circuit provides a discharge path between the bounding pad and the ground terminal and blocks a current path between the power terminal the ground terminal, and wherein the electrostatic discharge protection circuit comprises:
an electrostatic discharge detection circuit detecting whether the electrostatic discharge event occurs at the bounding pad to generate a first detection signal;
a discharge circuit receiving the first detection signal, wherein when the electrostatic discharge event occurs at the bounding pad, the discharge circuit provides the discharge path according to the first detection signal;
a first N-type transistor having a first terminal coupled to the core circuit, a second terminal coupled to the ground terminal, and a control terminal receiving the first detection signal and;
a first P-type transistor having a first terminal coupled to the bounding pad, a second terminal coupled to the core circuit, and a control terminal,
wherein when the electrostatic discharge event occurs at the bounding pad, the first N-type transistor is turned off according to the first detection signal to block the current path, and
wherein when the core circuit does not operate in a normal operation mode, the control terminal of the first P-type transistor is in a floating state.
10. The integrated circuit as claimed in claim 9 , wherein the core circuit operates in the normal operation mode, the control terminal of the first P-type transistor receives a control signal.
11. The integrated circuit as claimed in claim 9 , wherein the electrostatic discharge protection circuit further comprises:
a buffer, coupled between the electrostatic discharge detection circuit and the control terminal of the first N-type transistor, receiving the first detection signal, generating a buffering signal according to the first detection signal, and providing the buffering signal to the control terminal of the first N-type transistor,
wherein when the electrostatic discharge event occurs at the bounding pad, the first N-type transistor is turned off according to the buffering signal to block the current path.
12. The integrated circuit as claimed in claim 11 , wherein the buffer circuit comprises:
a second P-type transistor having a first terminal coupled to the bounding terminal, a second terminal coupled to a first node, and a control terminal receiving the first detection signal;
a second N-type transistor having a first terminal coupled to the first node, a second terminal coupled to the ground terminal, and a control terminal receiving the first detection signal;
a third P-type transistor having a first terminal coupled to the bounding terminal, a second terminal coupled to a second node, and a control terminal coupled to the first node; and
a third N-type transistor having a first terminal coupled to the second node, a second terminal coupled to the ground terminal, and a control terminal coupled to the first node;
wherein the buffering signal is generated at the second node.
13. The integrated circuit as claimed in claim 9 , wherein the discharge circuit generates a second detection signal which is inverse to the first detection signal, and the electrostatic discharge protection circuit further comprises:
an inverter, coupled between the discharge circuit and the control terminal of the first N-type transistor, receiving the second detection signal, generating an inverted signal according to the second detection signal, and providing the inverted signal to the control terminal of the first N-type transistor,
wherein when the electrostatic discharge event occurs at the bounding pad, the first N-type transistor is turned off according to the inverted signal to block the current path.
14. The integrated circuit as claimed in claim 9 , wherein the electrostatic discharge protection circuit further comprises:
an inverter, coupled between the electrostatic discharge detection circuit and the control terminal of the first N-type transistor, receiving the first detection signal, generating an inverted signal according to the first detection signal, and providing the inverted signal to the control terminal of the first N-type transistor,
wherein when the electrostatic discharge event occurs at the bounding pad, the first N-type transistor is turned off according to the inverted signal to block the current path.
15. The integrated circuit as claimed in claim 14 , wherein the electrostatic discharge detection circuit comprises:
a capacitor coupled between the bounding pad and a first node; and
a resistor coupled between the first node and the ground terminal,
wherein the first detection signal is generated at the first node.